On 5/26/26 16:57, Alex Deucher wrote: > Applied. Thanks! > > On Mon, May 25, 2026 at 7:39 AM Timur Kristóf <[email protected]> wrote: >> >> It seems that Pitcairn has the same issues as Tahiti >> with regards to the TLB size. This commit fixes a >> VCE1 FW validation timeout on suspend/resume on Pitcairn. >> >> Signed-off-by: Timur Kristóf <[email protected]> >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c >> index 02f85802f579..cd0fd77578d1 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c >> @@ -203,7 +203,7 @@ int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr >> *mgr, >> int r; >> >> /* Align to TLB L2 cache entry size to work around "V bit HW bug" */ >> - if (adev->asic_type == CHIP_TAHITI) { >> + if (adev->family == AMDGPU_FAMILY_SI) { >> alignment = 32 * 1024 / AMDGPU_GPU_PAGE_SIZE; >> num_pages = ALIGN(num_pages, alignment); >> } >> -- >> 2.54.0 >> >
Hi Alex, I can't find this patch in the amd-staging-drm-next branch or any other recent branch in your Gitlab repo on freedesktop.org. I hope it didn't get lost? I think this should land in kernel 7.1 before the release. Thanks, Viktor
