We should only increase the deferred errors in UMC block
Signed-off-by: Ce Sun <[email protected]>
---
drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c | 7 ++++++-
drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h | 4 ++++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c
b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c
index 210fbd8851a6..31ac5cda9cb5 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c
@@ -77,6 +77,10 @@ static bool aca_check_bank_hwip(struct aca_bank_reg *bank,
enum aca_ecc_hwip typ
if (!hwip->hwid)
return false;
+ /* Parse all deferred errors with UMC aca handle */
+ if (ACA_BANK_ERR_IS_DEFFERED(bank))
+ return type == ACA_ECC_HWIP__UMC;
+
ipid = bank->regs[ACA_REG_IDX__IPID];
hwid = ACA_REG_IPID_HARDWAREID(ipid);
mcatype = ACA_REG_IPID_MCATYPE(ipid);
@@ -178,7 +182,8 @@ static bool aca_check_umc_de(struct ras_core_context
*ras_core, uint64_t mc_umc_
{
return (ras_core->poison_supported &&
ACA_REG_STATUS_VAL(mc_umc_status) &&
- ACA_REG_STATUS_DEFERRED(mc_umc_status));
+ (ACA_REG_STATUS_DEFERRED(mc_umc_status) ||
+ ACA_REG_STATUS_POISON(mc_umc_status)));
}
static bool aca_check_umc_ue(struct ras_core_context *ras_core, uint64_t
mc_umc_status)
diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h
b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h
index 40e5d94b037f..c4c136d4c3f3 100644
--- a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h
+++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h
@@ -67,5 +67,9 @@
#define mmSMNXCD_XCD0_MCA_SMU 0x40430400 /* SMN XCD XCD0 */
#define mmSMNAID_AID0_MCA_SMU 0x03b30400 /* SMN AID AID0 */
+#define ACA_BANK_ERR_IS_DEFFERED(bank) \
+ (ACA_REG_STATUS_POISON((bank)->regs[ACA_REG_IDX_STATUS]) || \
+ ACA_REG_STATUS_DEFERRED((bank)->regs[ACA_REG_IDX_STATUS]))
+
extern const struct ras_aca_ip_func ras_aca_func_v1_0;
#endif
--
2.34.1