AMD General + /* The IP block decode of consumption is SMU */ + if (hwid != UMC_HWID_V12_0 || mcatype != UMC_MCATYPE_V12_0) + return false; + else + return true;
Alternatively, you can use return (hwid != UMC_HWID_V12_0 || mcatype != UMC_MCATYPE_V12_0) ? false : true; The series is Reviewed-by: Hawking Zhang <[email protected]> Regards, Hawking -----Original Message----- From: Sun, Ce(Overlord) <[email protected]> Sent: Tuesday, June 2, 2026 4:43 PM To: [email protected] Cc: Zhang, Hawking <[email protected]>; Chai, Thomas <[email protected]>; Zhou1, Tao <[email protected]>; Yang, Stanley <[email protected]>; Sun, Ce(Overlord) <[email protected]> Subject: [PATCH v1 2/3] drm/amdgpu/ras: Add IPID filtering for bad page recording Add IPID decoding macros and filter out SMU decoded IP blocks Signed-off-by: Ce Sun <[email protected]> --- drivers/gpu/drm/amd/ras/rascore/ras_umc.c | 5 ++++- drivers/gpu/drm/amd/ras/rascore/ras_umc.h | 1 + .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.c | 20 ++++++++++++++++++- .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.h | 9 +++++++++ 4 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c index e5971c3dd7da..cff6245d8add 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c @@ -270,7 +270,10 @@ int ras_umc_log_bad_bank(struct ras_core_context *ras_core, struct ras_bank_ecc struct ras_umc *ras_umc = &ras_core->ras_umc; struct eeprom_umc_record umc_rec; struct eeprom_umc_record *err_rec; - int ret; + int ret = 0; + + if (!ras_umc->ip_func->mca_ipid_check(bank)) + return ret; memset(&umc_rec, 0, sizeof(umc_rec)); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h index 237525b46b9b..4a693865a9be 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h @@ -110,6 +110,7 @@ struct ras_umc_ip_func { uint64_t soc_pa, struct umc_bank_addr *bank_addr); void (*mca_ipid_parse)(struct ras_core_context *ras_core, uint64_t ipid, uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid); + bool (*mca_ipid_check)(struct ras_bank_ecc *bank); }; struct eeprom_store_record { diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c index b809a2f21d73..a272e0d80cdb 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c @@ -356,11 +356,28 @@ static int convert_bank_to_nps_addr(struct ras_core_context *ras_core, return ret; } +static bool umc_v12_0_mca_ipid_check(struct ras_bank_ecc *bank) { + uint16_t hwid, mcatype; + + hwid = ACA_IPID_2_HWID(bank->ipid); + mcatype = ACA_IPID_2_MCATYPE(bank->ipid); + + /* The IP block decode of consumption is SMU */ + if (hwid != UMC_HWID_V12_0 || mcatype != UMC_MCATYPE_V12_0) + return false; + else + return true; +} + static int umc_v12_0_bank_to_eeprom_record(struct ras_core_context *ras_core, struct ras_bank_ecc *bank, struct eeprom_umc_record *record) { struct umc_phy_addr nps_addr; - int ret; + int ret = 0; + + if (!umc_v12_0_mca_ipid_check(bank)) + return ret; memset(&nps_addr, 0, sizeof(nps_addr)); @@ -524,5 +541,6 @@ const struct ras_umc_ip_func ras_umc_func_v12_0 = { .bank_to_soc_pa = umc_12_0_bank_to_soc_pa, .soc_pa_to_bank = umc_12_0_soc_pa_to_bank, .mca_ipid_parse = umc_v12_0_mca_ipid_parse, + .mca_ipid_check = umc_v12_0_mca_ipid_check, }; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h index 8a35ad856165..51459b5ec06e 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h @@ -287,6 +287,12 @@ #define ACA_ADDR_2_ERR_ADDR(addr) \ REG_GET_FIELD(addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr) +#define ACA_IPID_2_HWID(ipid) \ + REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID) + +#define ACA_IPID_2_MCATYPE(ipid) \ + REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType) + /* R13 bit shift should be considered, double the number */ #define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL (UMC_V12_0_NA_MAP_PA_NUM * 2) @@ -306,6 +312,9 @@ /* one device has 192GB HBM */ #define SOCKET_LFB_SIZE 0x3000000000ULL +#define UMC_HWID_V12_0 0x96 +#define UMC_MCATYPE_V12_0 0x0 + extern const struct ras_umc_ip_func ras_umc_func_v12_0; int ras_umc_get_badpage_count(struct ras_core_context *ras_core); -- 2.34.1
