From: Ovidiu Bunea <[email protected]> [why & how] There is an issue that is seemingly limited to DCN42 where systems with IOMMU enabled will hang during reboot stress testing. The hang happens shortly after DCN PG exit happens and HUBP is programmed for the first flip, but before the first surface address is latched. Testing has shown that disabling DCCG_GLOBAL_FGCG_REP_DIS, HUBP_FGCG_REP_DIS, and DCFCLK_GATE_DIS can mask this issue.
Disable FGCG for these three repeater bits to avoid issue while debug is on-going. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Ovidiu Bunea <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c | 6 +++++- drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c | 6 ++++++ drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 9 ++++++++- .../drm/amd/display/dc/resource/dcn42/dcn42_resource.c | 1 + 5 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d5d9d56fbcb8..d74776802418 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1288,6 +1288,7 @@ struct dc_debug_options { unsigned int min_deep_sleep_dcfclk_khz; unsigned int force_odm2to1_for_edp_pixclk_mhz; bool enable_replay_esd_recovery; + uint8_t iommu_mismatch_temp_wka; }; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c index e57242f8bc12..adc453c81831 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c @@ -81,8 +81,12 @@ void dccg42_enable_global_fgcg(struct dccg *dccg, bool value) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (dccg->ctx->dc->debug.disable_clock_gate) + /* Temporary workaround for IOMMU mismatch issue. + * Fine grain control via bit2 of debug flag. + */ + if (dccg->ctx->dc->debug.disable_clock_gate || (dccg->ctx->dc->debug.iommu_mismatch_temp_wka & 0x4)) value = false; + REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value); } diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c index e4602c3ddc66..57de98444f6c 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c @@ -20,6 +20,12 @@ static void hubp42_set_fgcg(struct hubp *hubp, bool enable) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + /* Temporary workaround for IOMMU mismatch issue. + * Fine grain control via bit1 of debug flag. + */ + if (hubp->ctx->dc->debug.iommu_mismatch_temp_wka & 0x2) + enable = false; + REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c index 664004cadf10..96e0133880e1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -70,6 +70,7 @@ void dcn42_init_hw(struct dc *dc) uint32_t user_level = MAX_BACKLIGHT_LEVEL; bool dchub_ref_freq_changed; int current_dchub_ref_freq = 0; + uint8_t dcfclk_gate_dis_value = 0; if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) { dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); @@ -243,7 +244,13 @@ void dcn42_init_hw(struct dc *dc) /* enable all DCN clock gating */ REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); + /* Temporary workaround for IOMMU mismatch issue. + * Fine grain control via bit0 of debug flag. + */ + if (dc->debug.iommu_mismatch_temp_wka & 0x1) + dcfclk_gate_dis_value = 1; + + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, dcfclk_gate_dis_value); } dcn401_setup_hpo_hw_control(hws, true); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index 7de12b16d7ad..eb7fe5d70264 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -801,6 +801,7 @@ static const struct dc_debug_options debug_defaults_drv = { .replay_skip_crtc_disabled = true, .psr_skip_crtc_disable = true, .force_odm2to1_for_edp_pixclk_mhz = 0, // disable the policy for now + .iommu_mismatch_temp_wka = 0x7, }; static const struct dc_check_config config_defaults = { -- 2.54.0
