On Mon, Jun 15, 2026 at 10:44 AM Jesse Zhang <[email protected]> wrote: > > Queue reset is not supported when running as an SR-IOV virtual > function on gfx11 dGPUs. Guard HSA_CAP_PER_QUEUE_RESET_SUPPORTED > with !amdgpu_sriov_vf() so the capability is not reported to user > space under SR-IOV, matching the gfx9/gfx10 path. > > Fixes: afc0c16db999 ("drm/amdkfd: Add queue reset support on gfx11 dGPU") > > Signed-off-by: Amber Lin <[email protected]> > Reviewed-by: Jesse Zhang <[email protected]>
Acked-by: Alex Deucher <[email protected]> For a future patch we should probably look at doing something like we do for kernel queues for KFD. E.g., amdgpu_ring_is_reset_type_supported() so we can clean up all of these IP version checks in common code. Alex > --- > drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > index a9879cf8539e..6a90a3ece9ed 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c > @@ -2020,9 +2020,10 @@ static void kfd_topology_set_capabilities(struct > kfd_topology_device *dev) > dev->node_props.debug_prop |= > HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 | > HSA_DBG_WATCH_ADDR_MASK_HI_BIT; > /* gfx11 dGPU */ > - if (KFD_GC_VERSION(dev->gpu) == IP_VERSION(11, 0, 0) || > - KFD_GC_VERSION(dev->gpu) == IP_VERSION(11, 0, 2) || > - KFD_GC_VERSION(dev->gpu) == IP_VERSION(11, 0, 3)) > + if ((KFD_GC_VERSION(dev->gpu) == IP_VERSION(11, 0, 0) || > + KFD_GC_VERSION(dev->gpu) == IP_VERSION(11, 0, 2) || > + KFD_GC_VERSION(dev->gpu) == IP_VERSION(11, 0, 3)) && > + !amdgpu_sriov_vf(dev->gpu->adev)) > dev->node_props.capability |= > HSA_CAP_PER_QUEUE_RESET_SUPPORTED; > > if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(12, 0, 0)) > -- > 2.49.0 >
