On Wed, Jun 10, 2026 at 11:58 PM Jesse Zhang <[email protected]> wrote: > > From: Alex Deucher <[email protected]>
Once again, feel free to take ownership of these. You did most of the work. Reviewed-by: Alex Deucher <[email protected]> > > Call the new userq reset helper, and dispatch KQs first by ring_id > before falling back to the user-queue lookup. > > v2: squash in fixes > > Signed-off-by: Alex Deucher <[email protected]> > Co-developed-by: Jesse Zhang <[email protected]> > Signed-off-by: Jesse Zhang <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 33 +++++++++++++++++++------- > 1 file changed, 24 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > index 380ba062134e..cb4d84c5f52b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c > @@ -5009,22 +5009,30 @@ static int gfx_v12_0_set_priv_inst_fault_state(struct > amdgpu_device *adev, > static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev, > struct amdgpu_iv_entry *entry) > { > - u8 me_id, pipe_id, queue_id; > - struct amdgpu_ring *ring; > - int i; > - > - me_id = (entry->ring_id & 0x0c) >> 2; > - pipe_id = (entry->ring_id & 0x03) >> 0; > - queue_id = (entry->ring_id & 0x70) >> 4; > + u32 doorbell_offset = entry->src_data[0] & > AMDGPU_CTXID0_DOORBELL_ID_MASK; > > + /* > + * Try KQ first by ring_id; UQ as fallback. KCQ and UQ never share > + * a HW slot (compute_hqd_mask contract). > + */ > if (!adev->gfx.disable_kq) { > + u8 me_id, pipe_id, queue_id; > + struct amdgpu_ring *ring; > + int i; > + > + me_id = (entry->ring_id & 0x0c) >> 2; > + pipe_id = (entry->ring_id & 0x03) >> 0; > + queue_id = (entry->ring_id & 0x70) >> 4; > + > switch (me_id) { > case 0: > for (i = 0; i < adev->gfx.num_gfx_rings; i++) { > ring = &adev->gfx.gfx_ring[i]; > if (ring->me == me_id && ring->pipe == > pipe_id && > - ring->queue == queue_id) > + ring->queue == queue_id) { > drm_sched_fault(&ring->sched); > + return; > + } > } > break; > case 1: > @@ -5032,8 +5040,10 @@ static void gfx_v12_0_handle_priv_fault(struct > amdgpu_device *adev, > for (i = 0; i < adev->gfx.num_compute_rings; i++) { > ring = &adev->gfx.compute_ring[i]; > if (ring->me == me_id && ring->pipe == > pipe_id && > - ring->queue == queue_id) > + ring->queue == queue_id) { > drm_sched_fault(&ring->sched); > + return; > + } > } > break; > default: > @@ -5041,6 +5051,11 @@ static void gfx_v12_0_handle_priv_fault(struct > amdgpu_device *adev, > break; > } > } > + > + /* No KQ matched: HW slot is a MES-scheduled user queue. */ > + if (adev->enable_mes && doorbell_offset) > + amdgpu_userq_process_reset_irq(adev, entry->pasid, > + doorbell_offset); > } > > static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev, > -- > 2.49.0 >
