retire legacy RAS reset/query operations for jpeg v4.0.3
Signed-off-by: Ce Sun <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 88 ------------------------
1 file changed, 88 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 8438e13d96a4..9993aee8b63a 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -1313,92 +1313,6 @@ const struct amdgpu_ip_block_version
jpeg_v4_0_3_ip_block = {
.funcs = &jpeg_v4_0_3_ip_funcs,
};
-static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[]
= {
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S,
regVCN_UE_ERR_STATUS_HI_JPEG0S),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D,
regVCN_UE_ERR_STATUS_HI_JPEG0D),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S,
regVCN_UE_ERR_STATUS_HI_JPEG1S),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D,
regVCN_UE_ERR_STATUS_HI_JPEG1D),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S,
regVCN_UE_ERR_STATUS_HI_JPEG2S),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D,
regVCN_UE_ERR_STATUS_HI_JPEG2D),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S,
regVCN_UE_ERR_STATUS_HI_JPEG3S),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D,
regVCN_UE_ERR_STATUS_HI_JPEG3D),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S,
regVCN_UE_ERR_STATUS_HI_JPEG4S),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D,
regVCN_UE_ERR_STATUS_HI_JPEG4D),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S,
regVCN_UE_ERR_STATUS_HI_JPEG5S),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D,
regVCN_UE_ERR_STATUS_HI_JPEG5D),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S,
regVCN_UE_ERR_STATUS_HI_JPEG6S),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D,
regVCN_UE_ERR_STATUS_HI_JPEG6D),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S,
regVCN_UE_ERR_STATUS_HI_JPEG7S),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"},
- {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D,
regVCN_UE_ERR_STATUS_HI_JPEG7D),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"},
-};
-
-static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev,
- uint32_t jpeg_inst,
- void *ras_err_status)
-{
- struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
-
- /* jpeg v4_0_3 only support uncorrectable errors */
- amdgpu_ras_inst_query_ras_error_count(adev,
- jpeg_v4_0_3_ue_reg_list,
- ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list),
- NULL, 0, GET_INST(VCN, jpeg_inst),
- AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
- &err_data->ue_count);
-}
-
-static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev,
- void *ras_err_status)
-{
- uint32_t i;
-
- if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) {
- dev_warn(adev->dev, "JPEG RAS is not supported\n");
- return;
- }
-
- for (i = 0; i < adev->jpeg.num_jpeg_inst; i++)
- jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status);
-}
-
-static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev,
- uint32_t jpeg_inst)
-{
- amdgpu_ras_inst_reset_ras_error_count(adev,
- jpeg_v4_0_3_ue_reg_list,
- ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list),
- GET_INST(VCN, jpeg_inst));
-}
-
-static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev)
-{
- uint32_t i;
-
- if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) {
- dev_warn(adev->dev, "JPEG RAS is not supported\n");
- return;
- }
-
- for (i = 0; i < adev->jpeg.num_jpeg_inst; i++)
- jpeg_v4_0_3_inst_reset_ras_error_count(adev, i);
-}
-
static uint32_t jpeg_v4_0_3_query_poison_by_instance(struct amdgpu_device
*adev,
uint32_t instance, uint32_t sub_block)
{
@@ -1437,8 +1351,6 @@ static bool jpeg_v4_0_3_query_ras_poison_status(struct
amdgpu_device *adev)
}
static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = {
- .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count,
- .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count,
.query_poison_status = jpeg_v4_0_3_query_ras_poison_status,
};
--
2.34.1
