Trivial compaction of some repetitive code: add/remove: 0/0 grow/shrink: 0/9 up/down: 0/-2326 (-2326) Function old new delta gfx_v11_0_read_wave_data 548 345 -203 gfx_v9_0_read_wave_data 583 379 -204 gfx_v10_0_read_wave_data 580 364 -216 gfx_v8_0_read_wave_data 1098 843 -255 gfx_v7_0_read_wave_data 1098 843 -255 gfx_v6_0_read_wave_data 1098 843 -255 gfx_v12_0_read_wave_data 804 497 -307 gfx_v12_1_read_wave_data 880 572 -308 gfx_v9_4_3_read_wave_data 760 437 -323 Total: Before=9992345, After=9990019, chg -0.02%
Signed-off-by: Tvrtko Ursulin <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 38 ++++++++++-------- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 36 +++++++++-------- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 52 +++++++++++++------------ drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 52 +++++++++++++------------ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 44 +++++++++++---------- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 44 +++++++++++---------- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 44 +++++++++++---------- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 36 +++++++++-------- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 36 +++++++++-------- 9 files changed, 209 insertions(+), 173 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 76d4c33a6e65..272968b82dee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4497,6 +4497,8 @@ static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { + u32 *_dst = dst; + /* in gfx10 the SIMD_ID is specified as part of the INSTANCE * field when performing a select_se_sh so it should be * zero here @@ -4504,23 +4506,25 @@ static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id WARN_ON(simd != 0); /* type 2 wave data */ - dst[(*no_fields)++] = 2; - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); + *dst++ = 2; + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_M0); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); + + *no_fields += _dst - dst; } static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 6346f16c4e61..849724dca980 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1006,28 +1006,32 @@ static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { + u32 *_dst = dst; + /* in gfx11 the SIMD_ID is specified as part of the INSTANCE * field when performing a select_se_sh so it should be * zero here */ WARN_ON(simd != 0); /* type 3 wave data */ - dst[(*no_fields)++] = 3; - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); + *dst++ = 3; + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_M0); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); + + *no_fields += _dst - dst; } static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index f8280cc81a66..f646b93da2c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -846,36 +846,40 @@ static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { + u32 *_dst = dst; + /* in gfx12 the SIMD_ID is specified as part of the INSTANCE * field when performing a select_se_sh so it should be * zero here */ WARN_ON(simd != 0); /* type 4 wave data */ - dst[(*no_fields)++] = 4; - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); + *dst++ = 4; + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_M0); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); + *dst++ = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); + + *no_fields += _dst - dst; } static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 30a38190f98a..af5a20475182 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -657,36 +657,40 @@ static void gfx_v12_1_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { + u32 *_dst = dst; + /* in gfx12 the SIMD_ID is specified as part of the INSTANCE * field when performing a select_se_sh so it should be * zero here */ WARN_ON(simd != 0); /* type 4 wave data */ - dst[(*no_fields)++] = 4; - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATUS); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID1); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID2); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_GPR_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_LDS_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS2); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_DBG1); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_M0); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_MODE); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATE_PRIV); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_USER); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_TRAP_CTRL); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_ACTIVE); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_VALID_AND_IDLE); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_SCHED_MODE); + *dst++ = 4; + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATUS); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_LO); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_HI); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_LO); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_HI); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID1); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID2); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_GPR_ALLOC); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_LDS_ALLOC); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS2); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_DBG1); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_M0); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_MODE); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATE_PRIV); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_USER); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_TRAP_CTRL); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_ACTIVE); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_VALID_AND_IDLE); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); + *dst++ = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_SCHED_MODE); + + *no_fields += _dst - dst; } static void gfx_v12_1_read_wave_sgprs(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index ac90d8e9d86a..01ec83896a25 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3033,27 +3033,31 @@ static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { + u32 *_dst = dst; + /* type 0 wave data */ - dst[(*no_fields)++] = 0; - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); + *dst++ = 0; + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); + + *no_fields += _dst - dst; } static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 65b8497ad5f0..e30bec91b3a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4034,27 +4034,31 @@ static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { + u32 *_dst = dst; + /* type 0 wave data */ - dst[(*no_fields)++] = 0; - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); + *dst++ = 0; + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); + + *no_fields += _dst - dst; } static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 130196859ff3..f92c9c696d78 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5183,27 +5183,31 @@ static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { + u32 *_dst = dst; + /* type 0 wave data */ - dst[(*no_fields)++] = 0; - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); + *dst++ = 0; + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); + + *no_fields += _dst - dst; } static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index f836621c46eb..95c93131ebe1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1954,23 +1954,27 @@ static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { + u32 *_dst = dst; + /* type 1 wave data */ - dst[(*no_fields)++] = 1; - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); - dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); + *dst++ = 1; + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); + *dst++ = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); + + *no_fields += _dst - dst; } static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 71a2558acef8..16d9a4b1f091 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -742,23 +742,27 @@ static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) { + u32 *_dst = dst; + /* type 1 wave data */ - dst[(*no_fields)++] = 1; - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); - dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); + *dst++ = 1; + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); + *dst++ = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); + + *no_fields += _dst - dst; } static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, -- 2.54.0
