#include "amdgpu_sa.h"
#include "amdgpu_uid.h"
#include "amdgpu_video_codecs.h"
@@ -609,44 +609,6 @@ struct amd_powerplay {
(rid == 0x01) || \
(rid == 0x10))))
-enum amdgpu_mqd_update_flag {
- AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1,
- AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2,
- AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */
-};
-
-struct amdgpu_mqd_prop {
- uint64_t mqd_gpu_addr;
- uint64_t hqd_base_gpu_addr;
- uint64_t rptr_gpu_addr;
- uint64_t wptr_gpu_addr;
- uint32_t queue_size;
- bool use_doorbell;
- uint32_t doorbell_index;
- uint64_t eop_gpu_addr;
- uint32_t hqd_pipe_priority;
- uint32_t hqd_queue_priority;
- uint32_t mqd_stride_size;
- bool allow_tunneling;
- bool hqd_active;
- uint64_t shadow_addr;
- uint64_t gds_bkup_addr;
- uint64_t csa_addr;
- uint64_t fence_address;
- bool tmz_queue;
- bool kernel_queue;
- uint32_t *cu_mask;
- uint32_t cu_mask_count;
- uint32_t cu_flags;
- bool is_user_cu_masked;
-};
-
-struct amdgpu_mqd {
- unsigned mqd_size;
- int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
- struct amdgpu_mqd_prop *p);
-};
-
struct amdgpu_pcie_reset_ctx {
bool in_link_reset;
bool occurs_dpc;
@@ -1034,14 +996,6 @@ struct amdgpu_device {
struct amdgpu_kfd_dev kfd;
};
-/*
- * MES FW uses address(mqd_addr + sizeof(struct mqd) +
3*sizeof(uint32_t))
- * as fence address and writes a 32 bit fence value to this address.
- * Driver needs to allocate at least 4 DWs extra memory in addition to
- * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE
for safety.
- */
-#define AMDGPU_MQD_SIZE_ALIGN(mqd_size)
AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32))
-
static inline uint32_t amdgpu_ip_version(const struct
amdgpu_device *adev,
uint8_t ip, uint8_t inst)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 5255360353f4..7b4cfb5c8f83 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -438,6 +438,52 @@ struct amdgpu_mes_funcs {
struct mes_inv_tlbs_pasid_input *input);
};
+enum amdgpu_mqd_update_flag {
+ AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1,
+ AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2,
+ AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */
+};
+
+struct amdgpu_mqd_prop {
+ uint64_t mqd_gpu_addr;
+ uint64_t hqd_base_gpu_addr;
+ uint64_t rptr_gpu_addr;
+ uint64_t wptr_gpu_addr;
+ uint32_t queue_size;
+ bool use_doorbell;
+ uint32_t doorbell_index;
+ uint64_t eop_gpu_addr;
+ uint32_t hqd_pipe_priority;
+ uint32_t hqd_queue_priority;
+ uint32_t mqd_stride_size;
+ bool allow_tunneling;
+ bool hqd_active;
+ uint64_t shadow_addr;
+ uint64_t gds_bkup_addr;
+ uint64_t csa_addr;
+ uint64_t fence_address;
+ bool tmz_queue;
+ bool kernel_queue;
+ uint32_t *cu_mask;
+ uint32_t cu_mask_count;
+ uint32_t cu_flags;
+ bool is_user_cu_masked;
+};
+
+struct amdgpu_mqd {
+ unsigned mqd_size;
+ int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
+ struct amdgpu_mqd_prop *p);
+};
+
+/*
+ * MES FW uses address(mqd_addr + sizeof(struct mqd) +
3*sizeof(uint32_t))
+ * as fence address and writes a 32 bit fence value to this address.
+ * Driver needs to allocate at least 4 DWs extra memory in addition to
+ * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE
for safety.
+ */
+#define AMDGPU_MQD_SIZE_ALIGN(mqd_size)
AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32))
+
#define amdgpu_mes_kiq_hw_init(adev, xcc_id) \
(adev)->mes.kiq_hw_init((adev), (xcc_id))
#define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \
