retire legacy RAS reset/query operations for sdma v4_4_2
Signed-off-by: Ce Sun <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 28 ------
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 104 +----------------------
2 files changed, 1 insertion(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 2bf365609775..4f4e56022c97 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -85,34 +85,6 @@ struct amdgpu_sdma_instance {
const struct amdgpu_sdma_funcs *funcs;
};
-enum amdgpu_sdma_ras_memory_id {
- AMDGPU_SDMA_MBANK_DATA_BUF0 = 1,
- AMDGPU_SDMA_MBANK_DATA_BUF1 = 2,
- AMDGPU_SDMA_MBANK_DATA_BUF2 = 3,
- AMDGPU_SDMA_MBANK_DATA_BUF3 = 4,
- AMDGPU_SDMA_MBANK_DATA_BUF4 = 5,
- AMDGPU_SDMA_MBANK_DATA_BUF5 = 6,
- AMDGPU_SDMA_MBANK_DATA_BUF6 = 7,
- AMDGPU_SDMA_MBANK_DATA_BUF7 = 8,
- AMDGPU_SDMA_MBANK_DATA_BUF8 = 9,
- AMDGPU_SDMA_MBANK_DATA_BUF9 = 10,
- AMDGPU_SDMA_MBANK_DATA_BUF10 = 11,
- AMDGPU_SDMA_MBANK_DATA_BUF11 = 12,
- AMDGPU_SDMA_MBANK_DATA_BUF12 = 13,
- AMDGPU_SDMA_MBANK_DATA_BUF13 = 14,
- AMDGPU_SDMA_MBANK_DATA_BUF14 = 15,
- AMDGPU_SDMA_MBANK_DATA_BUF15 = 16,
- AMDGPU_SDMA_UCODE_BUF = 17,
- AMDGPU_SDMA_RB_CMD_BUF = 18,
- AMDGPU_SDMA_IB_CMD_BUF = 19,
- AMDGPU_SDMA_UTCL1_RD_FIFO = 20,
- AMDGPU_SDMA_UTCL1_RDBST_FIFO = 21,
- AMDGPU_SDMA_UTCL1_WR_FIFO = 22,
- AMDGPU_SDMA_DATA_LUT_FIFO = 23,
- AMDGPU_SDMA_SPLIT_DAT_BUF = 24,
- AMDGPU_SDMA_MEMORY_BLOCK_LAST,
-};
-
struct amdgpu_sdma_ras {
struct amdgpu_ras_block_object ras_block;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 0d7e22060a92..484f1a6b5fbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -2416,111 +2416,9 @@ struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
.resume = &sdma_v4_4_2_xcp_resume
};
-static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[]
= {
- {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO,
regSDMA_UE_ERR_STATUS_HI),
- 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
-};
-
-static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] =
{
- {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"},
- {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"},
- {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"},
- {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"},
- {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"},
- {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"},
- {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"},
- {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"},
- {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"},
- {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"},
- {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"},
- {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"},
- {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"},
- {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"},
- {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"},
- {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"},
- {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"},
- {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"},
- {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"},
- {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"},
- {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"},
- {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"},
- {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"},
- {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"},
-};
-
-static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,
- uint32_t sdma_inst,
- void *ras_err_status)
-{
- struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
- uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
- unsigned long ue_count = 0;
- struct amdgpu_smuio_mcm_config_info mcm_info = {
- .socket_id = adev->smuio.funcs->get_socket_id(adev),
- .die_id = adev->sdma.instance[sdma_inst].aid_id,
- };
-
- /* sdma v4_4_2 doesn't support query ce counts */
- amdgpu_ras_inst_query_ras_error_count(adev,
- sdma_v4_2_2_ue_reg_list,
- ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
- sdma_v4_4_2_ras_memory_list,
- ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),
- sdma_dev_inst,
- AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
- &ue_count);
-
- amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count);
-}
-
-static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,
- void *ras_err_status)
-{
- uint32_t inst_mask;
- int i = 0;
-
- inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
- if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
- for_each_inst(i, inst_mask)
- sdma_v4_4_2_inst_query_ras_error_count(adev, i,
ras_err_status);
- } else {
- dev_warn(adev->dev, "SDMA RAS is not supported\n");
- }
-}
-
-static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev,
- uint32_t sdma_inst)
-{
- uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
-
- amdgpu_ras_inst_reset_ras_error_count(adev,
- sdma_v4_2_2_ue_reg_list,
- ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
- sdma_dev_inst);
-}
-
-static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev)
-{
- uint32_t inst_mask;
- int i = 0;
-
- inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
- if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
- for_each_inst(i, inst_mask)
- sdma_v4_4_2_inst_reset_ras_error_count(adev, i);
- } else {
- dev_warn(adev->dev, "SDMA RAS is not supported\n");
- }
-}
-
-static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {
- .query_ras_error_count = sdma_v4_4_2_query_ras_error_count,
- .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
-};
-
static struct amdgpu_sdma_ras sdma_v4_4_2_ras = {
.ras_block = {
- .hw_ops = &sdma_v4_4_2_ras_hw_ops,
+ .hw_ops = NULL,
},
};
--
2.34.1
