Remove the legacy logic that skips eeprom writes for PMFW-managed RAS data
Signed-off-by: Ce Sun <[email protected]>
---
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 43 +------------------
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 3 --
2 files changed, 1 insertion(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index d28e8958b0ff..80de2459c76a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -124,8 +124,6 @@
RAS_TABLE_V2_1_INFO_SIZE) \
/ RAS_TABLE_RECORD_SIZE)
-#define RAS_SMU_MESSAGE_TIMEOUT_MS 1000 /* 1s */
-
/* Given a zero-based index of an EEPROM RAS record, yields the EEPROM
* offset off of RAS_TABLE_START. That is, this is something you can
* add to control->i2c_address, and then tell I2C layer to read
@@ -878,44 +876,6 @@ amdgpu_ras_eeprom_update_header(struct
amdgpu_ras_eeprom_control *control)
return res;
}
-int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control
*control)
-{
- struct amdgpu_device *adev = to_amdgpu_device(control);
- int ret, retry = 20;
-
- if (!amdgpu_ras_smu_eeprom_supported(adev))
- return 0;
-
- control->ras_num_recs_old = control->ras_num_recs;
-
- do {
- /* 1000ms timeout is long enough, smu_get_badpage_count won't
- * return -EBUSY before timeout.
- */
- ret = amdgpu_ras_smu_get_badpage_count(adev,
- &(control->ras_num_recs), RAS_SMU_MESSAGE_TIMEOUT_MS);
- if (!ret &&
- (control->ras_num_recs_old == control->ras_num_recs)) {
- /* record number update in PMFW needs some time,
- * smu_get_badpage_count may return immediately without
- * count update, sleep for a while and retry again.
- */
- msleep(50);
- retry--;
- } else {
- break;
- }
- } while (retry);
-
- /* no update of record number is not a real failure,
- * don't print warning here
- */
- if (!ret && (control->ras_num_recs_old == control->ras_num_recs))
- ret = -EINVAL;
-
- return ret;
-}
-
/**
* amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table
* @control: pointer to control structure
@@ -934,11 +894,10 @@ int amdgpu_ras_eeprom_append(struct
amdgpu_ras_eeprom_control *control,
const u32 num)
{
struct amdgpu_device *adev = to_amdgpu_device(control);
- struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
int res, i;
uint64_t nps = AMDGPU_NPS1_PARTITION_MODE;
- if (!__is_ras_eeprom_supported(adev) || !con)
+ if (!__is_ras_eeprom_supported(adev))
return 0;
if (num == 0) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
index a62114800a92..3c7fcce5fe8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
@@ -82,7 +82,6 @@ struct amdgpu_ras_eeprom_control {
/* Number of records in the table.
*/
u32 ras_num_recs;
- u32 ras_num_recs_old;
/* the bad page number is ras_num_recs or
* ras_num_recs * umc.retire_unit
@@ -191,8 +190,6 @@ int amdgpu_ras_eeprom_read_idx(struct
amdgpu_ras_eeprom_control *control,
struct eeprom_table_record *record, u32 rec_idx,
const u32 num);
-int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control
*control);
-
void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev);
extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops;
--
2.34.1
