This is needed to allocate occlusion counters across both gfx pipes. No functional change since we only use one gfx pipe at the moment (default value is 1).
Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index d171d41654980..5e7d0cd85c365 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -2178,6 +2178,9 @@ static void gfx_v11_0_constants_init(struct amdgpu_device *adev) tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); adev->gfx.config.ta_cntl2_truncate_coord_mode = REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); + /* program DB_RING_CONTROL for multiple GFX pipes */ + WREG32_FIELD15_PREREG(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL, + (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1); /* XXX SH_MEM regs */ /* where to put LDS, scratch, GPUVM in FSA64 space */ -- 2.54.0
