Add amdgpu_mes_rs64mem_init() and amdgpu_mes_rs64mem_fini() to manage the RS64 local memory context arrays used by the MES scheduler.
Signed-off-by: Prike Liang <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 44 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 7 ++++ 2 files changed, 51 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index c66e69b62361..8ba1c941c03d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -921,6 +921,50 @@ int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev) return r; } +/** + * amdgpu_mes_rs64mem_init - initialize RS64 local memory context arrays + * + * @mes: MES instance + * + * Returns 0 on success, negative errno on failure. + */ +int amdgpu_mes_rs64mem_init(struct amdgpu_mes *mes) +{ + struct amdgpu_device *adev = container_of(mes, struct amdgpu_device, mes); + int r; + + if (!mes->use_rs64mem) + return 0; + + r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, + &mes->ctx_array_size_bo, + &mes->ctx_array_size_gpu_addr, + (void **)&mes->ctx_array_size_cpu_ptr); + if (r) { + dev_err(adev->dev, + "Failed to allocate ctx array size BO, r=%d\n", r); + return r; + } + + memset(mes->ctx_array_size_cpu_ptr, 0, PAGE_SIZE); + + return 0; +} + +/** + * amdgpu_mes_rs64mem_fini - tear down RS64 local memory management + */ +void amdgpu_mes_rs64mem_fini(struct amdgpu_mes *mes) +{ + if (mes->ctx_array_size_bo) { + amdgpu_bo_free_kernel(&mes->ctx_array_size_bo, + &mes->ctx_array_size_gpu_addr, + (void **)&mes->ctx_array_size_cpu_ptr); + } + mes->use_rs64mem = false; +} + #if defined(CONFIG_DEBUG_FS) static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 389e3324caea..520bcd8ee202 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -171,6 +171,11 @@ struct amdgpu_mes { bool compute_pipe_reset_enabled; bool gfx_pipe_reset_enabled; + + bool use_rs64mem; + struct amdgpu_bo *ctx_array_size_bo; + uint64_t ctx_array_size_gpu_addr; + uint32_t *ctx_array_size_cpu_ptr; }; struct amdgpu_mes_hung_queue_hqd_info { @@ -617,4 +622,6 @@ bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev); int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); +int amdgpu_mes_rs64mem_init(struct amdgpu_mes *mes); +void amdgpu_mes_rs64mem_fini(struct amdgpu_mes *mes); #endif /* __AMDGPU_MES_H__ */ -- 2.34.1
