From: Fangzhi Zuo <[email protected]> [Why] On DCN32/321 sometimes DMCUB takes a long time to flush. This adds a delay before the data is available on the driver side even after driver receives notification from DMCUB via inbox
[How] Allocating DMUB memory to GTT gives much better latency. Limit this to DCN32/1 for now; it will be made general to all other dGPUs later. Reviewed-by: Aurabindo Pillai <[email protected]> Reviewed-by: Sun peng (Leo) Li <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Signed-off-by: George Zhang <[email protected]> --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c index 9d08a3055996..d2148b62073d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_dmub.c @@ -506,6 +506,7 @@ int dm_dmub_sw_init(struct amdgpu_device *adev) DMUB_WINDOW_MEMORY_TYPE_FB, /* DMUB_WINDOW_CURSOR_OFFLOAD */ }; int r; + int mem_domain = AMDGPU_GEM_DOMAIN_GTT; switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { case IP_VERSION(2, 1, 0): @@ -639,13 +640,19 @@ int dm_dmub_sw_init(struct amdgpu_device *adev) return -EINVAL; } + /* Limit to allocate dmub to GTT on DCN32/1 + * TODO: Other asics with GDDR7 may have worse latency + */ + if (dmub_asic != DMUB_ASIC_DCN32 && + dmub_asic != DMUB_ASIC_DCN321) + mem_domain |= AMDGPU_GEM_DOMAIN_VRAM; + /* * Allocate a framebuffer based on the total size of all the regions. * TODO: Move this into GART. */ r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_VRAM | - AMDGPU_GEM_DOMAIN_GTT, + mem_domain, &adev->dm.dmub_bo, &adev->dm.dmub_bo_gpu_addr, &adev->dm.dmub_bo_cpu_addr); -- 2.55.0
