Emit a compute CLEAR_STATE packet on the compute rings after the GFX ring already finished executing ME_INITIALIZE and before the ring test, so that gfx_v6_0_cp_gfx_resume() can wait until the CLEAR_STATE is complete.
For reference, see si_cp_start() in the old radeon driver. Signed-off-by: Timur Kristóf <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index eeada89bb31a..5b570a4b5c01 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -2263,6 +2263,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) for (i = 0; i < adev->gfx.num_compute_rings; i++) { ring = &adev->gfx.compute_ring[i]; + r = amdgpu_ring_alloc(ring, 2); + if (r) + return r; + + amdgpu_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_commit(ring); + r = amdgpu_ring_test_helper(ring); if (r) return r; -- 2.55.0
