This patch
1. Requests PSP to set UVD and JPEG SEC LVL reg incase of
fw_load_type is PSP_LOAD.
2. Set UVD and JPEG SEC LVL incase of backdoor loading and
non-secure-direct loading type.
3. To support this, PSP implementing new cmd id :
GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL, vcn/jpeg will call
this cmd to set sec lvl.
This will help to resolve jpeg/vcn ring/ib timeout while
accessing mmhub.
Signed-off-by: Suresh Guttula <[email protected]>
Reviewed-by: McRae Geoffrey<[email protected]>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 27 ++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c | 29 +++++++++++++++++
drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.h | 2 ++
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 31 +++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h | 2 ++
.../include/asic_reg/vcn/vcn_5_0_0_offset.h | 2 ++
.../include/asic_reg/vcn/vcn_5_3_0_offset.h | 2 ++
9 files changed, 97 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index a36cbfc1f6f1..64281553c6d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1222,6 +1222,33 @@ int psp_memory_partition(struct psp_context *psp, int
mode)
return ret;
}
+int psp_set_mmhub_eco_sec_level(struct amdgpu_device *adev)
+{
+ int ret;
+ struct psp_context *psp = &adev->psp;
+ struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
+
+ cmd->cmd_id = GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL;
+
+ ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
+ if (ret) {
+ dev_err(psp->adev->dev,
+ "PSP request failed to set mmuhub eco sec level with
ret=%d\n", ret);
+ release_psp_cmd_buf(psp);
+ return ret;
+ }
+
+ if (cmd->resp.status) {
+ dev_err(psp->adev->dev,
+ "MMHUB ECO SEC LEVEL command 0x%x failed, PSP response
status: 0x%X\n",
+ cmd->cmd_id, cmd->resp.status);
+ ret = -EIO;
+ }
+ release_psp_cmd_buf(psp);
+
+ return ret;
+}
+
static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt,
uint32_t *ptl_fmt)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 2d838b1b2b11..3d7744d60fac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -656,5 +656,6 @@ int amdgpu_psp_reg_program_no_ring(struct psp_context *psp,
uint32_t val,
void amdgpu_psp_debugfs_init(struct amdgpu_device *adev);
int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode,
enum psp_gfx_fw_type *type);
+int psp_set_mmhub_eco_sec_level(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
index 66d4c487eee5..9468b4541b5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c
@@ -399,6 +399,30 @@ static void jpeg_v5_3_0_stop_dpg_mode(struct amdgpu_device
*adev, int inst_idx)
WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
}
+/**
+ * jpeg_v5_3_0_set_mmhub_eco_sec_level - set jpeg sec lvl reg
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Set jpeg sec lvl based on load type
+ */
+static int jpeg_v5_3_0_set_mmhub_eco_sec_level(struct amdgpu_device *adev)
+{
+ int r = 0;
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ //Request to PSP to program JPEG secure lvl register
+ r = psp_set_mmhub_eco_sec_level(adev);
+ } else {
+ //Program UVD_JMC_JPEG_SECURE_LVL register
+ //During brinrup phase or backdoor loading case, updating
register here
+ //to avoid dependency on PSP
+ WREG32_SOC15(JPEG, 0, regUVD_JMC_JPEG_SECURE_LVL,
vcnipUVD_JMC_JPEG_SECURE_LVL);
+ }
+
+ return r;
+}
+
/**
* jpeg_v5_3_0_start - start JPEG block
*
@@ -424,6 +448,11 @@ static int jpeg_v5_3_0_start(struct amdgpu_device *adev)
if (r)
return r;
+ /* program JPEG secure lvl register */
+ r = jpeg_v5_3_0_set_mmhub_eco_sec_level(adev);
+ if (r)
+ return r;
+
/* JPEG disable CGC */
jpeg_v5_3_0_disable_clock_gating(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.h
b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.h
index c1e7537d0f18..ef6376f3a79b 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.h
@@ -30,6 +30,8 @@
#define vcnipUVD_NO_OP 0x0029
#define vcnipJPEG_DEC_GFX10_ADDR_CONFIG 0x404A
+#define vcnipUVD_JMC_JPEG_SECURE_LVL 0x22
+
extern const struct amdgpu_ip_block_version jpeg_v5_3_0_ip_block;
#endif /* __JPEG_V5_0_0_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index ac34bac3c839..ad618b78685f 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -110,6 +110,7 @@ enum psp_gfx_cmd_id
GFX_CMD_ID_PERF_HW = 0x0000004C, /* performance monitor */
GFX_CMD_ID_FB_FW_RESERV_ADDR = 0x00000050, /* Query FW reservation addr
*/
GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR = 0x00000051, /* Query FW reservation
extended addr */
+ GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL = 0x0000005D, /* Set MMHUB ECO sec
lvls on VCN block */
};
/* PSP boot config sub-commands */
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 45580e9c4e0c..1318e731440b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -795,6 +795,32 @@ static int vcn_v5_0_0_start_dpg_mode(struct
amdgpu_vcn_inst *vinst,
return 0;
}
+/**
+ * vcn_v5_0_0_set_mmhub_eco_sec_level - set vcn sec lvl reg
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Set vcn sec lvl based on load type
+ */
+static int vcn_v5_0_0_set_mmhub_eco_sec_level(struct amdgpu_device *adev)
+{
+ int r = 0;
+
+ if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(5, 3, 0)) {
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ //Request to PSP to program VCN secure lvl register
+ r = psp_set_mmhub_eco_sec_level(adev);
+ } else {
+ //Program UVD_MC_VID_SECURE_LVL register
+ //During brinrup phase or backdoor loading case,
updating register here
+ //to avoid dependency on PSP
+ WREG32_SOC15(VCN, 0, regUVD_MC_VID_SECURE_LVL,
UVD_MC_VID_SECURE_LVL);
+ }
+ }
+
+ return r;
+}
+
/**
* vcn_v5_0_0_start - VCN start
*
@@ -819,6 +845,11 @@ static int vcn_v5_0_0_start(struct amdgpu_vcn_inst *vinst)
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+ /* program VCN secure lvl register */
+ r = vcn_v5_0_0_set_mmhub_eco_sec_level(adev);
+ if (r)
+ return r;
+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
return vcn_v5_0_0_start_dpg_mode(vinst,
adev->vcn.inst[i].indirect_sram);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h
b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h
index 51bbccd4360f..9ae2bed990be 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h
@@ -32,6 +32,8 @@
#define VCN_VID_IP_ADDRESS 0x0
#define VCN_AON_IP_ADDRESS 0x30000
+#define UVD_MC_VID_SECURE_LVL 0x22222222
+
extern const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block;
#endif /* __VCN_V5_0_0_H__ */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
index 72a118b2af69..a7e64e304ffa 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
@@ -1027,6 +1027,8 @@
#define regCC_UVD_VCPU_ERR_INST_ADDR_LO_BASE_IDX
1
#define regCC_UVD_VCPU_ERR_INST_ADDR_HI
0x0035
#define regCC_UVD_VCPU_ERR_INST_ADDR_HI_BASE_IDX
1
+#define regUVD_MC_VID_SECURE_LVL
0x0037
+#define regUVD_MC_VID_SECURE_LVL_BASE_IDX
1
#define regUVD_LMI_MMSCH_NC_SPACE
0x003d
#define regUVD_LMI_MMSCH_NC_SPACE_BASE_IDX
1
#define regUVD_LMI_ATOMIC_SPACE
0x003e
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h
index 1051a788c9d7..da5acac08ae9 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h
@@ -162,6 +162,8 @@
#define regCC_UVD_VCPU_ERR_INST_ADDR_LO_BASE_IDX
1
#define regCC_UVD_VCPU_ERR_INST_ADDR_HI
0x0035
#define regCC_UVD_VCPU_ERR_INST_ADDR_HI_BASE_IDX
1
+#define regUVD_JMC_JPEG_SECURE_LVL
0x0036
+#define regUVD_JMC_JPEG_SECURE_LVL_BASE_IDX
1
#define regUVD_LMI_MMSCH_NC_SPACE
0x003d
#define regUVD_LMI_MMSCH_NC_SPACE_BASE_IDX
1
#define regUVD_LMI_ATOMIC_SPACE
0x003e
--
2.43.0
