Not sure what that should originally been good for, but it doesn't seem to make any sense any more.
Signed-off-by: Christian König <[email protected]> --- drivers/gpu/drm/amd/amdgpu/cik.c | 40 +++++++++++++++++----------------- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 8 +++---- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 ++++----- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 38 ++++++++++++++++---------------- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++---- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 18 +++++++-------- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +++---- drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 12 +++++----- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 20 ++++++++--------- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 +++---- drivers/gpu/drm/amd/amdgpu/si.c | 34 ++++++++++++++--------------- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vi.c | 10 ++++----- 15 files changed, 113 insertions(+), 113 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 793b1470284d..6128080ff662 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -757,72 +757,72 @@ static void cik_init_golden_registers(struct amdgpu_device *adev) case CHIP_BONAIRE: amdgpu_program_register_sequence(adev, bonaire_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init)); + ARRAY_SIZE(bonaire_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, bonaire_golden_registers, - (const u32)ARRAY_SIZE(bonaire_golden_registers)); + ARRAY_SIZE(bonaire_golden_registers)); amdgpu_program_register_sequence(adev, bonaire_golden_common_registers, - (const u32)ARRAY_SIZE(bonaire_golden_common_registers)); + ARRAY_SIZE(bonaire_golden_common_registers)); amdgpu_program_register_sequence(adev, bonaire_golden_spm_registers, - (const u32)ARRAY_SIZE(bonaire_golden_spm_registers)); + ARRAY_SIZE(bonaire_golden_spm_registers)); break; case CHIP_KABINI: amdgpu_program_register_sequence(adev, kalindi_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); + ARRAY_SIZE(kalindi_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, kalindi_golden_registers, - (const u32)ARRAY_SIZE(kalindi_golden_registers)); + ARRAY_SIZE(kalindi_golden_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_common_registers, - (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); + ARRAY_SIZE(kalindi_golden_common_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_spm_registers, - (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); + ARRAY_SIZE(kalindi_golden_spm_registers)); break; case CHIP_MULLINS: amdgpu_program_register_sequence(adev, kalindi_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); + ARRAY_SIZE(kalindi_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, godavari_golden_registers, - (const u32)ARRAY_SIZE(godavari_golden_registers)); + ARRAY_SIZE(godavari_golden_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_common_registers, - (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); + ARRAY_SIZE(kalindi_golden_common_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_spm_registers, - (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); + ARRAY_SIZE(kalindi_golden_spm_registers)); break; case CHIP_KAVERI: amdgpu_program_register_sequence(adev, spectre_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init)); + ARRAY_SIZE(spectre_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, spectre_golden_registers, - (const u32)ARRAY_SIZE(spectre_golden_registers)); + ARRAY_SIZE(spectre_golden_registers)); amdgpu_program_register_sequence(adev, spectre_golden_common_registers, - (const u32)ARRAY_SIZE(spectre_golden_common_registers)); + ARRAY_SIZE(spectre_golden_common_registers)); amdgpu_program_register_sequence(adev, spectre_golden_spm_registers, - (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); + ARRAY_SIZE(spectre_golden_spm_registers)); break; case CHIP_HAWAII: amdgpu_program_register_sequence(adev, hawaii_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init)); + ARRAY_SIZE(hawaii_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, hawaii_golden_registers, - (const u32)ARRAY_SIZE(hawaii_golden_registers)); + ARRAY_SIZE(hawaii_golden_registers)); amdgpu_program_register_sequence(adev, hawaii_golden_common_registers, - (const u32)ARRAY_SIZE(hawaii_golden_common_registers)); + ARRAY_SIZE(hawaii_golden_common_registers)); amdgpu_program_register_sequence(adev, hawaii_golden_spm_registers, - (const u32)ARRAY_SIZE(hawaii_golden_spm_registers)); + ARRAY_SIZE(hawaii_golden_spm_registers)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index f3dd6b7bfd4d..a397111c2ced 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -147,18 +147,18 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index be25706e5f07..67e670989e81 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -156,26 +156,26 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, - (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + ARRAY_SIZE(cz_golden_settings_a11)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, - (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + ARRAY_SIZE(stoney_golden_settings_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, polaris11_golden_settings_a11, - (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); + ARRAY_SIZE(polaris11_golden_settings_a11)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, polaris10_golden_settings_a11, - (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); + ARRAY_SIZE(polaris10_golden_settings_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index a74515aba1f6..1512325af117 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -681,53 +681,53 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, - (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + ARRAY_SIZE(golden_settings_iceland_a11)); amdgpu_program_register_sequence(adev, iceland_golden_common_all, - (const u32)ARRAY_SIZE(iceland_golden_common_all)); + ARRAY_SIZE(iceland_golden_common_all)); break; case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); amdgpu_program_register_sequence(adev, fiji_golden_common_all, - (const u32)ARRAY_SIZE(fiji_golden_common_all)); + ARRAY_SIZE(fiji_golden_common_all)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); amdgpu_program_register_sequence(adev, tonga_golden_common_all, - (const u32)ARRAY_SIZE(tonga_golden_common_all)); + ARRAY_SIZE(tonga_golden_common_all)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + ARRAY_SIZE(golden_settings_polaris11_a11)); amdgpu_program_register_sequence(adev, polaris11_golden_common_all, - (const u32)ARRAY_SIZE(polaris11_golden_common_all)); + ARRAY_SIZE(polaris11_golden_common_all)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + ARRAY_SIZE(golden_settings_polaris10_a11)); amdgpu_program_register_sequence(adev, polaris10_golden_common_all, - (const u32)ARRAY_SIZE(polaris10_golden_common_all)); + ARRAY_SIZE(polaris10_golden_common_all)); WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); if (adev->pdev->revision == 0xc7 && ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || @@ -740,24 +740,24 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, - (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + ARRAY_SIZE(cz_golden_settings_a11)); amdgpu_program_register_sequence(adev, cz_golden_common_all, - (const u32)ARRAY_SIZE(cz_golden_common_all)); + ARRAY_SIZE(cz_golden_common_all)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, - (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + ARRAY_SIZE(stoney_golden_settings_a11)); amdgpu_program_register_sequence(adev, stoney_golden_common_all, - (const u32)ARRAY_SIZE(stoney_golden_common_all)); + ARRAY_SIZE(stoney_golden_common_all)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 9855dc03744f..637c06df5db4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -226,18 +226,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, golden_settings_gc_9_0, - (const u32)ARRAY_SIZE(golden_settings_gc_9_0)); + ARRAY_SIZE(golden_settings_gc_9_0)); amdgpu_program_register_sequence(adev, golden_settings_gc_9_0_vg10, - (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); + ARRAY_SIZE(golden_settings_gc_9_0_vg10)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_gc_9_1, - (const u32)ARRAY_SIZE(golden_settings_gc_9_1)); + ARRAY_SIZE(golden_settings_gc_9_1)); amdgpu_program_register_sequence(adev, golden_settings_gc_9_1_rv1, - (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1)); + ARRAY_SIZE(golden_settings_gc_9_1_rv1)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 583d87792820..6c6a7e14359c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -69,10 +69,10 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, - (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + ARRAY_SIZE(golden_settings_iceland_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 9ca5fea93ebc..edbe0df24d90 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -122,42 +122,42 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + ARRAY_SIZE(golden_settings_polaris11_a11)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_stoney_common, - (const u32)ARRAY_SIZE(golden_settings_stoney_common)); + ARRAY_SIZE(golden_settings_stoney_common)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 0de4dc068516..91fc097abdfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -687,15 +687,15 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, golden_settings_mmhub_1_0_0, - (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0)); + ARRAY_SIZE(golden_settings_mmhub_1_0_0)); amdgpu_program_register_sequence(adev, golden_settings_athub_1_0_0, - (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); + ARRAY_SIZE(golden_settings_athub_1_0_0)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_athub_1_0_0, - (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); + ARRAY_SIZE(golden_settings_athub_1_0_0)); break; default: break; @@ -715,7 +715,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) amdgpu_program_register_sequence(adev, golden_settings_vega10_hdp, - (const u32)ARRAY_SIZE(golden_settings_vega10_hdp)); + ARRAY_SIZE(golden_settings_vega10_hdp)); if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index 2b435c02ef44..df52824c0cd4 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -281,29 +281,29 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, xgpu_fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, xgpu_fiji_golden_settings_a10, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_fiji_golden_settings_a10)); amdgpu_program_register_sequence(adev, xgpu_fiji_golden_common_all, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_fiji_golden_common_all)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, xgpu_tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, xgpu_tonga_golden_settings_a11, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_tonga_golden_settings_a11)); amdgpu_program_register_sequence(adev, xgpu_tonga_golden_common_all, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_tonga_golden_common_all)); break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 92f8c44a73b6..121e628e7cdb 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -95,10 +95,10 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, - (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + ARRAY_SIZE(golden_settings_iceland_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 52e6bf2e9e59..c8c93f9dac21 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -194,45 +194,45 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + ARRAY_SIZE(golden_settings_polaris11_a11)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, - (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + ARRAY_SIZE(cz_golden_settings_a11)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, - (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + ARRAY_SIZE(stoney_golden_settings_a11)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index fe78c00b9ffa..a0a5a8da4c4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -132,18 +132,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, golden_settings_sdma_4, - (const u32)ARRAY_SIZE(golden_settings_sdma_4)); + ARRAY_SIZE(golden_settings_sdma_4)); amdgpu_program_register_sequence(adev, golden_settings_sdma_vg10, - (const u32)ARRAY_SIZE(golden_settings_sdma_vg10)); + ARRAY_SIZE(golden_settings_sdma_vg10)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_sdma_4_1, - (const u32)ARRAY_SIZE(golden_settings_sdma_4_1)); + ARRAY_SIZE(golden_settings_sdma_4_1)); amdgpu_program_register_sequence(adev, golden_settings_sdma_rv1, - (const u32)ARRAY_SIZE(golden_settings_sdma_rv1)); + ARRAY_SIZE(golden_settings_sdma_rv1)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 8284d5dbfc30..49eef3090f08 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1392,63 +1392,63 @@ static void si_init_golden_registers(struct amdgpu_device *adev) case CHIP_TAHITI: amdgpu_program_register_sequence(adev, tahiti_golden_registers, - (const u32)ARRAY_SIZE(tahiti_golden_registers)); + ARRAY_SIZE(tahiti_golden_registers)); amdgpu_program_register_sequence(adev, tahiti_golden_rlc_registers, - (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers)); + ARRAY_SIZE(tahiti_golden_rlc_registers)); amdgpu_program_register_sequence(adev, tahiti_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init)); + ARRAY_SIZE(tahiti_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, tahiti_golden_registers2, - (const u32)ARRAY_SIZE(tahiti_golden_registers2)); + ARRAY_SIZE(tahiti_golden_registers2)); break; case CHIP_PITCAIRN: amdgpu_program_register_sequence(adev, pitcairn_golden_registers, - (const u32)ARRAY_SIZE(pitcairn_golden_registers)); + ARRAY_SIZE(pitcairn_golden_registers)); amdgpu_program_register_sequence(adev, pitcairn_golden_rlc_registers, - (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers)); + ARRAY_SIZE(pitcairn_golden_rlc_registers)); amdgpu_program_register_sequence(adev, pitcairn_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); + ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); break; case CHIP_VERDE: amdgpu_program_register_sequence(adev, verde_golden_registers, - (const u32)ARRAY_SIZE(verde_golden_registers)); + ARRAY_SIZE(verde_golden_registers)); amdgpu_program_register_sequence(adev, verde_golden_rlc_registers, - (const u32)ARRAY_SIZE(verde_golden_rlc_registers)); + ARRAY_SIZE(verde_golden_rlc_registers)); amdgpu_program_register_sequence(adev, verde_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init)); + ARRAY_SIZE(verde_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, verde_pg_init, - (const u32)ARRAY_SIZE(verde_pg_init)); + ARRAY_SIZE(verde_pg_init)); break; case CHIP_OLAND: amdgpu_program_register_sequence(adev, oland_golden_registers, - (const u32)ARRAY_SIZE(oland_golden_registers)); + ARRAY_SIZE(oland_golden_registers)); amdgpu_program_register_sequence(adev, oland_golden_rlc_registers, - (const u32)ARRAY_SIZE(oland_golden_rlc_registers)); + ARRAY_SIZE(oland_golden_rlc_registers)); amdgpu_program_register_sequence(adev, oland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); + ARRAY_SIZE(oland_mgcg_cgcg_init)); break; case CHIP_HAINAN: amdgpu_program_register_sequence(adev, hainan_golden_registers, - (const u32)ARRAY_SIZE(hainan_golden_registers)); + ARRAY_SIZE(hainan_golden_registers)); amdgpu_program_register_sequence(adev, hainan_golden_registers2, - (const u32)ARRAY_SIZE(hainan_golden_registers2)); + ARRAY_SIZE(hainan_golden_registers2)); amdgpu_program_register_sequence(adev, hainan_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init)); + ARRAY_SIZE(hainan_mgcg_cgcg_init)); break; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 4e67fe1e7955..fa27e0354f35 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -265,12 +265,12 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, vega10_golden_init, - (const u32)ARRAY_SIZE(vega10_golden_init)); + ARRAY_SIZE(vega10_golden_init)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, raven_golden_init, - (const u32)ARRAY_SIZE(raven_golden_init)); + ARRAY_SIZE(raven_golden_init)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 3a4c2fa7e36d..bb8ca9489546 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -284,27 +284,27 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); break; case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); break; case CHIP_POLARIS11: case CHIP_POLARIS10: -- 2.11.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
