AMD General
________________________________ From: Liang, Prike <[email protected]> Sent: Tuesday, July 28, 2026 8:53 AM To: [email protected] <[email protected]> Cc: Deucher, Alexander <[email protected]>; Koenig, Christian <[email protected]>; Chen, Michael <[email protected]>; Liu, Shaoyun <[email protected]>; Liang, Prike <[email protected]> Subject: [PATCH 2/2] drm/amdkfd: enable rs64mem for kfd queue Enabled RS64mem for KFD queues by integrating process and gang context index allocation. Signed-off-by: Prike Liang <[email protected]> --- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 25 ++++++++++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +++ 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 51ee9c39104b..ce0ca3445ccd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -210,8 +210,10 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; struct kfd_process_device *pdd = qpd_to_pdd(qpd); struct mes_add_queue_input queue_input; + struct amdgpu_mes *mes = &adev->mes; int r, queue_type; uint64_t wptr_addr_off; + uint32_t index; if (!dqm->sched_running || dqm->sched_halt) return 0; @@ -265,9 +267,18 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, queue_input.vm_cntx_cntl = qpd->vm_cntx_cntl; queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; - amdgpu_mes_lock(&adev->mes); - r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); - amdgpu_mes_unlock(&adev->mes); + if (mes->use_rs64mem) { + amdgpu_mes_alloc_proc_ctx_index(mes, &index); + pdd->proc_ctx_array_index = index; + queue_input.process_context_array_index = index; + amdgpu_mes_alloc_gang_ctx_index(mes, &index); + pdd->gang_ctx_array_index = index; + queue_input.gang_context_array_index = index; + } Looks like you allocate one unique proc_ctx_array_index for each queue, but shouldn't all queues of the same process share one index? + + amdgpu_mes_lock(mes); + r = adev->mes.funcs->add_hw_queue(mes, &queue_input); + amdgpu_mes_unlock(mes); up_read(&adev->reset_domain->sem); if (r) { dev_err(adev->dev, "failed to add hardware queue to MES, doorbell=0x%x\n", @@ -287,6 +298,8 @@ static int remove_queue_mes_on_reset_option(struct device_queue_manager *dqm, st struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; int r; struct mes_remove_queue_input queue_input; + struct kfd_process_device *pdd = qpd_to_pdd(qpd); + struct amdgpu_mes *mes = &adev->mes; /* queue was already removed during reset */ if (q->properties.is_reset) @@ -303,10 +316,16 @@ static int remove_queue_mes_on_reset_option(struct device_queue_manager *dqm, st queue_input.queue_type = convert_to_amdgpu_ring_type(q->properties.type); queue_input.remove_queue_after_reset = flush_mes_queue; queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; + queue_input.gang_context_array_index = pdd->gang_ctx_array_index; amdgpu_mes_lock(&adev->mes); r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); amdgpu_mes_unlock(&adev->mes); + if (mes->use_rs64mem) { + amdgpu_mes_free_proc_ctx_index(mes, pdd->proc_ctx_array_index); + amdgpu_mes_free_gang_ctx_index(mes, pdd->gang_ctx_array_index); + } + up_read(&adev->reset_domain->sem); /* If is_for_reset set, it is a mes internal cleanup */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 88191a4c1657..c1bbae9e6e82 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -871,6 +871,9 @@ struct kfd_process_device { uint64_t proc_ctx_gpu_addr; void *proc_ctx_cpu_ptr; + uint32_t proc_ctx_array_index; + uint32_t gang_ctx_array_index; + /* Tracks queue reset status */ bool has_reset_queue; -- 2.34.1
