From: Harry Wentland <[email protected]>
commit 76a2db58e95e328007043f54ac3c7336ccbee440 upstream.
dcn32_update_clocks_update_dtb_dto() reprograms the DTB DTO of every
timing generator in the context whenever the DTBCLK reference changes,
passing a zeroed pixel rate and never setting is_hdmi.
dccg32_set_dtbclk_dto() treats a zero pixel rate as a disable request,
and that branch drives PIPE_DTO_SRC_SEL to the DP DTO source. A timing
generator actively scanning out an HDMI stream therefore has its pixel
rate source re-muxed out from under the live raster, and the OTG stops
on the spot.
Two displays where only one runs a 128b/132b link hit this reliably.
is_dtbclk_required() holds the DTBCLK reference high while both are
active, and the moment the 128b/132b stream is torn down (compositor
switch, display disable, hot-unplug) the next safe_to_lower pass drops
the reference to the lowest DPM level and the DTO walk freezes the
surviving screen. On Navi31 the DAL mailbox then goes deaf on the
DISPCLK hard-min that follows the walk in dcn32_update_clocks(),
stranding both SMU mailboxes until reboot.
Set is_hdmi for HDMI and DVI signals so the disable path leaves the
pixel rate source selection on the HDMI path, and pass the real pixel
rate for 128b/132b streams so a reference change rescales their DTO
instead of disabling it.
Fixes: 128c1ca0303f ("drm/amd/display: Update DTBCLK for DCN32")
Signed-off-by: Harry Wentland <[email protected]>
Reviewed-by: Fangzhi Zuo <[email protected]>
Tested-by: Dan Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[ mschwartz: dcn32 clk_mgr hunk only, as 6.6.y predates the dcn35
clk_mgr. The rest is HDMI FRL enablement, absent before 7.2, so the
FRL conditions and the req_audio_dtbclk_khz assignment they guard are
dropped and the FRL-centric changelog is rewritten. Added the
pipe_ctx->stream check the new dereferences need. ]
Signed-off-by: Matthew Schwartz <[email protected]>
---
6.6.y predates the dcn35 clk_mgr, so only the dcn32 hunk applies. The
6.12.y, 6.18.y and 7.1.y equivalent is sent alongside this one. Tested
on Navi31 with a DisplayPort UHBR monitor and an HDMI TV.
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 084994c650c4..285689d7ecc4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -276,13 +276,20 @@ static void dcn32_update_clocks_update_dtb_dto(struct
clk_mgr_internal *clk_mgr,
struct dtbclk_dto_params dto_params = {0};
/* use mask to program DTO once per tg */
- if (pipe_ctx->stream_res.tg &&
+ if (pipe_ctx->stream && pipe_ctx->stream_res.tg &&
!(tg_mask & (1 <<
pipe_ctx->stream_res.tg->inst))) {
tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
+ if
(dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))
+ dto_params.pixclk_khz =
pipe_ctx->stream->timing.pix_clk_100hz / 10;
+
+ if (dc_is_hdmi_signal(pipe_ctx->stream->signal) ||
+
dc_is_dvi_signal(pipe_ctx->stream->signal))
+ dto_params.is_hdmi = true;
+
dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
//dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg,
&dto_params);
}
--
2.50.1
