From: Harry VanZyllDeJong <[email protected]> [Why] VRR info packet previously only supported up to 10-bit refresh rate values limiting the range of FreeSync minimum and maximum refresh rates that could be encoded.
[How] Expanded the bit masking in PB11/PB12 from 2 to 4 bits to capture bits 11:8 of the minimum and maximum FreeSync refresh rates, enabling the VRR info packet to encode 12-bit refresh rate values. Reviewed-by: Anthony Koo <[email protected]> Signed-off-by: Harry VanZyllDeJong <[email protected]> Signed-off-by: Roman Li <[email protected]> --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index f3b41087678b..4bd060e30799 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -684,11 +684,11 @@ static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr, /* PB8 = FreeSync Maximum refresh rate (Hz) */ infopacket->sb[8] = max_refresh & 0xFF; - /* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */ - infopacket->sb[11] = (min_programmed >> 8) & 0x03; + /* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 11:8 */ + infopacket->sb[11] = (min_programmed >> 8) & 0x0F; - /* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */ - infopacket->sb[12] = (max_refresh >> 8) & 0x03; + /* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 11:8 */ + infopacket->sb[12] = (max_refresh >> 8) & 0x0F; /* PB16 : Reserved bits 7:1, FixedRate bit 0 */ infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0; -- 2.34.1
