Avoid hardcode, get the parameters from amdgpu. For the algorithms of ras address conversion and die id calculation, not only pa, (pa + pa_base) is also needed.
Signed-off-by: Tao Zhou <[email protected]> --- drivers/gpu/drm/amd/ras/core/ras.h | 4 ++++ drivers/gpu/drm/amd/ras/core/ras_umc.c | 7 +++++-- drivers/gpu/drm/amd/ras/core/ras_umc.h | 7 ++++++- drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c | 20 ++++++++++++------- drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.h | 3 --- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 2 ++ 6 files changed, 30 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/core/ras.h b/drivers/gpu/drm/amd/ras/core/ras.h index d61c977b07cf..e0ed6a3ce168 100644 --- a/drivers/gpu/drm/amd/ras/core/ras.h +++ b/drivers/gpu/drm/amd/ras/core/ras.h @@ -278,6 +278,10 @@ struct ras_psp_config { struct ras_umc_config { uint32_t umc_vram_type; uint32_t num_umc; + /* socket xgmi offset, base address of umc physical address */ + uint64_t pa_base; + /* local frame buffer size */ + uint64_t lfb_size; }; struct ras_eeprom_config { diff --git a/drivers/gpu/drm/amd/ras/core/ras_umc.c b/drivers/gpu/drm/amd/ras/core/ras_umc.c index 95a98b411fc7..2dc1c0b6ac49 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/core/ras_umc.c @@ -411,8 +411,9 @@ static int ras_umc_eeprom_rec2nps_addr_legacy(struct ras_core_context *ras_core, * only ever existed on NPS1 systems) */ if (ras_core->ras_umc.ip_func && ras_core->ras_umc.ip_func->get_die_id) { - die_id = ras_core->ras_umc.ip_func->get_die_id(record->address, - RAS_PFN_TO_ADDR(EEPROM_RECORD_UMC_ADDR_PFN(record))); + die_id = ras_core->ras_umc.ip_func->get_die_id(ras_core, + record->address, + RAS_PFN_TO_ADDR(EEPROM_RECORD_UMC_ADDR_PFN(record))); } else { RAS_DEV_ERR(ras_core->dev, "get_die_id is not supported!\n"); return -EOPNOTSUPP; @@ -855,6 +856,8 @@ int ras_umc_hw_init(struct ras_core_context *ras_core) ras_umc->umc_vram_type); return -ENODATA; } + ras_umc->pa_base = ras_core->config->umc_cfg.pa_base; + ras_umc->lfb_size = ras_core->config->umc_cfg.lfb_size; ras_umc->umc_ip_version = ras_core->config->umc_ip_version; ras_umc->ip_func = ras_umc_get_ip_func(ras_core, ras_umc->umc_ip_version); diff --git a/drivers/gpu/drm/amd/ras/core/ras_umc.h b/drivers/gpu/drm/amd/ras/core/ras_umc.h index af76de70ddd1..13d715c8553f 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_umc.h +++ b/drivers/gpu/drm/amd/ras/core/ras_umc.h @@ -139,7 +139,8 @@ struct ras_umc_ip_func { uint32_t nps); uint64_t (*nps_pa_to_row_pa)(struct ras_core_context *ras_core, uint64_t pa, enum umc_memory_partition_mode nps, bool zero_pfn_ok); - uint32_t (*get_die_id)(uint64_t mca_addr, uint64_t pa); + uint32_t (*get_die_id)(struct ras_core_context *ras_core, + uint64_t mca_addr, uint64_t pa); }; struct eeprom_store_record { @@ -168,6 +169,10 @@ struct ras_umc { u32 umc_ip_version; u32 umc_vram_type; u32 num_umc; + /* socket xgmi offset, base address of umc physical address */ + u64 pa_base; + /* local frame buffer size */ + u64 lfb_size; const struct ras_umc_ip_func *ip_func; struct radix_tree_root root; struct mutex tree_lock; diff --git a/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c index ccdbc5c4bab1..4bf993325a3f 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c +++ b/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.c @@ -243,6 +243,8 @@ static int umc_v12_0_ma2pa(struct ras_core_context *ras_core, uint32_t socket_id = addr_in->socket_id; uint32_t channel_index; uint64_t err_addr = addr_in->err_addr; + uint64_t pa_base = ras_core->ras_umc.pa_base; + uint64_t lfb_size = ras_core->ras_umc.lfb_size; if (node_inst != UMC_INV_AID_NODE) { if (ch_inst >= UMC_V12_0_CHANNEL_INSTANCE_NUM || @@ -318,11 +320,11 @@ static int umc_v12_0_ma2pa(struct ras_core_context *ras_core, OFFSET_IN_256B_BLOCK(na); /* calc channel hash based on absolute address */ - soc_pa += socket_id * SOCKET_LFB_SIZE; + soc_pa += pa_base; /* the umc channel bits are not original values, they are hashed */ UMC_V12_0_SET_CHANNEL_HASH(channel_index, soc_pa); /* restore pa */ - soc_pa -= socket_id * SOCKET_LFB_SIZE; + soc_pa -= pa_base; /* get some channel bits from na_nps directly and * add nps section offset @@ -330,16 +332,16 @@ static int umc_v12_0_ma2pa(struct ras_core_context *ras_core, if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) { soc_pa &= ~(0x1ULL << UMC_V12_0_PA_CH5_BIT); soc_pa |= ((na_nps & 0x100) << 5); - soc_pa += (node_inst >> 1) * (SOCKET_LFB_SIZE >> 1); + soc_pa += (node_inst >> 1) * (lfb_size >> 1); } else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) { soc_pa &= ~(0x3ULL << UMC_V12_0_PA_CH4_BIT); soc_pa |= ((na_nps & 0x300) << 4); - soc_pa += node_inst * (SOCKET_LFB_SIZE >> 2); + soc_pa += node_inst * (lfb_size >> 2); } else if (nps == UMC_MEMORY_PARTITION_MODE_NPS8) { soc_pa &= ~(0x7ULL << UMC_V12_0_PA_CH4_BIT); soc_pa |= ((na_nps & 0x700) << 4); - soc_pa += node_inst * (SOCKET_LFB_SIZE >> 2) + - (channel_index >> 4) * (SOCKET_LFB_SIZE >> 3); + soc_pa += node_inst * (lfb_size >> 2) + + (channel_index >> 4) * (lfb_size >> 3); } addr_out->pa = soc_pa; @@ -496,10 +498,14 @@ static void umc_v12_0_mca_ipid_parse(struct ras_core_context *ras_core, uint64_t * umc number: 16 * hbm type: UMC_VRAM_TYPE_HBM */ -static uint32_t umc_v12_0_get_die_id(uint64_t mca_addr, uint64_t pa) +static uint32_t umc_v12_0_get_die_id(struct ras_core_context *ras_core, + uint64_t mca_addr, uint64_t pa) { uint32_t die = 0; + /* use absolute PA */ + pa += ras_core->ras_umc.pa_base; + /* we only calculate die id for nps1 mode(save_nps == ch_idx_v2 == 0) */ die += (((pa >> 12) & 0x1ULL) ^ ((pa >> 20) & 0x1ULL) ^ diff --git a/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.h b/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.h index 268db10dc6b0..f6f7f827e06f 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.h +++ b/drivers/gpu/drm/amd/ras/core/ras_umc_v12_0.h @@ -300,9 +300,6 @@ #define UMC_V12_0_TOTAL_CHANNEL_NUM \ (UMC_V12_0_AID_NUM_MAX * UMC_V12_0_UMC_INSTANCE_NUM * UMC_V12_0_CHANNEL_INSTANCE_NUM) -/* one device has 192GB HBM */ -#define SOCKET_LFB_SIZE 0x3000000000ULL - extern const struct ras_umc_ip_func ras_umc_func_v12_0; int ras_umc_get_badpage_count(struct ras_core_context *ras_core); diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index c55288c2df9a..c58fa0ef8a80 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -285,6 +285,8 @@ static int amdgpu_ras_mgr_init_umc_config(struct amdgpu_device *adev, umc_cfg->umc_vram_type = adev->gmc.vram_type; umc_cfg->num_umc = adev->gmc.num_umc; + umc_cfg->lfb_size = adev->gmc.xgmi.node_segment_size; + umc_cfg->pa_base = amdgpu_xgmi_get_relative_phy_addr(adev, 0x0ULL); return 0; } -- 2.34.1
