From: Taimur Hassan <[email protected]> This DC patchset brings improvements in multiple areas. In summary, we have:
* Reworked per-DPM derate handling: refactor the per-DPM derate logic, update derates with default per-DPM values, and move the soc_and_ip_translator onto the new per-DPM organization * DCN6 mode-support and UTM work: opt-out for the OutstandingRequests check, a utm_support capability flag, and a guard against an empty DCN6 UTM QoS table * More DMU/DMUB offload: send DPM0 clock values for Z8 retention, allow DCHVM<->rIOMMU SDP port disconnection on DCN42, and add the DC_BLS command * HWSS block-sequence cleanups: move periodic interrupt calculations to HWSS, drop pipe_ctx from HUBP_WAIT_FOR_DCC_META_PROP, use mpcc_id instead of the hubp instance, and add a wait stream regen event * DML updates: unify CalculateFlipSchedule logic and relax the frame size limit for the dcn5/6 core funcs files * clk_mgr refactor renaming carried DCE clock manager functions for dcn10, plus a missing-prototype build fix and a static DCN42 SOC BB struct * Expanded IGT/KUnit validation: CACP ACE curve area debugfs and cursor mode tests on disabled CRTCs * eDP fix to skip teardown while a forced PSR is active Acked-by: Tom Chung <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: James Lin <[email protected]> --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index edd6a113cfee..1355ce2b4970 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -66,7 +66,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.393" +#define DC_VER "3.2.394" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC -- 2.43.0
