On Wed, Aug 12, 2026 at 5:30 AM Jesse Zhang <[email protected]> wrote: > > The MES scheduler ring has no drm scheduler (no_scheduler = true), so it is > skipped by the force-completion loop in amdgpu_device_pre_asic_reset(). It > uses a polling fence whose hw value lives in wb (GTT) memory and survives a > MODE1 reset, while fence_drv.sync_seq keeps advancing for every packet. > > When the reset is triggered because MES itself stopped responding, the > timed-out packets advance sync_seq past the last hw fence value MES wrote. > After resume the first MES submission polls forever on a seq that is never > written back, failing the resume and wedging the box on a second reset: > > amdgpu: MES ring buffer is full. > amdgpu: *ERROR* ring gfx_0.0.0 test failed (-110) > amdgpu: resume of IP block <gfx_v11_0> failed -110 > amdgpu: GPU reset end with ret = -110 > > Force complete the MES scheduler ring fences together with the scheduler > rings so their hw fence is realigned to sync_seq. > > v2: cover all XCCs (one scheduler ring each), not just mes.ring[0]. > > Signed-off-by: Jesse Zhang <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> KIQ needs a similar fix. It also sets ring->no_scheduler = true. Alex > --- > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 520fd59036d5..e2b8253489f3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -5036,6 +5036,19 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device > *adev, > amdgpu_fence_driver_force_completion(ring, fence); > } > > + /* > + * MES scheduler rings have no drm scheduler, so they are missed by > the > + * loop above. Realign their polling fence too (one per XCC), > otherwise the > + * first post-reset submission polls forever on a stale seq. > sched.ready > + * skips KIQ pipes. > + */ > + for (i = 0; i < AMDGPU_MAX_MES_INST_PIPES; i++) { > + struct amdgpu_ring *mes_ring = &adev->mes.ring[i]; > + > + if (mes_ring->fence_drv.initialized && mes_ring->sched.ready) > + amdgpu_fence_driver_force_completion(mes_ring, fence); > + } > + > amdgpu_fence_driver_isr_toggle(adev, false); > > r = amdgpu_reset_prepare_hwcontext(adev, reset_context); > -- > 2.49.0 >
