From: YiPeng Chai <[email protected]> Update the dedicated smu ras message interface to accept multiple parameters on each call.
v2: Add input parameter validation. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Yang Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 25 ++++++++++++++++--- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 15 ++++++++--- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 7 ++++-- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c | 3 ++- .../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c | 9 ++++--- 5 files changed, 46 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index cca32f74abf02..649fdc4471487 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -641,7 +641,8 @@ bool is_support_cclk_dpm(struct amdgpu_device *adev) } int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, - uint32_t param, uint32_t *read_arg) + const uint32_t *params, size_t num_params, + uint32_t *read_args, size_t num_read_args) { struct smu_context *smu = adev->powerplay.pp_handle; int ret = -EOPNOTSUPP; @@ -649,12 +650,30 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms if (!smu) return ret; - if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) - ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); + if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) { + if (num_params && !params) + return -EINVAL; + + if (num_read_args && !read_args) + return -EINVAL; + + if (num_params > SMU_MSG_MAX_ARGS || num_read_args > SMU_MSG_MAX_ARGS) + return -EINVAL; + + ret = smu->ppt_funcs->ras_send_msg(smu, msg, + params, num_params, read_args, num_read_args); + } return ret; } +int amdgpu_smu_ras_send_msg_legacy(struct amdgpu_device *adev, + enum smu_message_type msg, uint32_t param, uint32_t *read_arg) +{ + return amdgpu_smu_ras_send_msg(adev, msg, ¶m, 1, + read_arg, read_arg ? 1 : 0); +} + int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, enum smu_feature_mask mask) { diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 00d075cb86b84..b77723f04268d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1626,9 +1626,15 @@ struct pptable_funcs { * ¶m: Message parameter. * &read_arg: SMU response (optional). */ - int (*ras_send_msg)(struct smu_context *smu, - enum smu_message_type msg, uint32_t param, uint32_t *read_arg); + int (*ras_send_msg)(struct smu_context *smu, enum smu_message_type msg, + const uint32_t *params, size_t num_params, + uint32_t *read_args, size_t num_read_args); + /** + * @get_ras_smu_drv: Get RAS smu driver interface + * Return: ras_smu_drv * + */ + int (*get_ras_smu_drv)(struct smu_context *smu, const struct ras_smu_drv **ras_smu_drv); /** * @set_power_dep: Create or destroy a power dependency link * from an integrated xHCI controller to the GPU so that the GPU is @@ -1985,7 +1991,10 @@ ssize_t smu_get_pm_policy_info(struct smu_context *smu, enum pp_pm_policy p_type, char *sysbuf); int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, - uint32_t param, uint32_t *readarg); + const uint32_t *params, size_t num_params, + uint32_t *read_args, size_t num_read_args); +int amdgpu_smu_ras_send_msg_legacy(struct amdgpu_device *adev, + enum smu_message_type msg, uint32_t param, uint32_t *read_arg); int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, enum smu_feature_mask mask); #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 39f5ed5da58f3..c31ee92d11ca4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -3219,7 +3219,9 @@ static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) return ret; } -static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_type msg, uint32_t param, uint32_t *read_arg) +static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_type msg, + const uint32_t *params, size_t num_params, + uint32_t *read_args, size_t num_read_args) { struct amdgpu_device *adev = smu->adev; int ret; @@ -3240,7 +3242,8 @@ static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_ty case SMU_MSG_GetTimestamp: case SMU_MSG_GetBadPageIpid: case SMU_MSG_EraseRasTable: - ret = smu_cmn_send_smc_msg_with_param(smu, msg, param, read_arg); + ret = smu_cmn_send_smc_msg_with_params(smu, msg, + params, num_params, read_args, num_read_args); break; default: ret = -EPERM; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c index b2d9148a36f99..698a373005092 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c @@ -56,7 +56,8 @@ static int amdgpu_ras_send_mp1_msg(struct ras_core_context *ras_core, return -EOPNOTSUPP; if (down_read_trylock(&adev->reset_domain->sem)) { - ret = amdgpu_smu_ras_send_msg(adev, smu_msg, param, read_arg); + ret = amdgpu_smu_ras_send_msg_legacy(adev, smu_msg, + param, read_arg); up_read(&adev->reset_domain->sem); } else { ret = -RAS_CORE_GPU_IN_MODE1_RESET; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c index 3c4575a5d902d..bc89a2ad75ef1 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c @@ -53,7 +53,7 @@ static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core, SMU_MSG_QueryValidMcaCeCount : SMU_MSG_QueryValidMcaCount; if (down_read_trylock(&adev->reset_domain->sem)) { - ret = amdgpu_smu_ras_send_msg(adev, smu_msg, 0, count); + ret = amdgpu_smu_ras_send_msg_legacy(adev, smu_msg, 0, count); up_read(&adev->reset_domain->sem); } else { ret = -RAS_CORE_GPU_IN_MODE1_RESET; @@ -80,7 +80,8 @@ static int mp1_v13_0_dump_valid_bank(struct ras_core_context *ras_core, offset = reg_idx * 8; for (i = 0; i < ARRAY_SIZE(data); i++) { param = ((idx & 0xffff) << 16) | ((offset + (i << 2)) & 0xfffc); - ret = amdgpu_smu_ras_send_msg(adev, smu_msg, param, &data[i]); + ret = amdgpu_smu_ras_send_msg_legacy(adev, smu_msg, + param, &data[i]); if (ret) { RAS_DEV_ERR(adev, "ACA failed to read register[%d], offset:0x%x\n", reg_idx, offset); @@ -105,7 +106,7 @@ static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core, int ret = 0; if (down_read_trylock(&adev->reset_domain->sem)) { - ret = amdgpu_smu_ras_send_msg(adev, + ret = amdgpu_smu_ras_send_msg_legacy(adev, pmfw_eeprom_msgs[index], param, read_arg); up_read(&adev->reset_domain->sem); } else { @@ -138,7 +139,7 @@ static int mp1_v13_0_set_debug_mode(struct ras_core_context *ras_core, bool enab int ret; u32 smu_msg = SMU_MSG_ClearMcaOnRead; - ret = amdgpu_smu_ras_send_msg(adev, smu_msg, + ret = amdgpu_smu_ras_send_msg_legacy(adev, smu_msg, enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK, NULL); return ret; -- 2.55.0
