From: Sridevi Arvindekar <[email protected]> [Why&How] Updates and fixes to HPO functionality, initialization, encoder configuration and platform-specific behavior.
Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Sridevi Arvindekar <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 7 ++++++ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 12 +++++++++- drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 7 +++--- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 6 +++++ .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 5 +++- .../display/dc/link/hwss/link_hwss_hpo_dp.c | 23 ++++++++++--------- .../dc/link/protocols/link_dp_capability.c | 3 ++- 7 files changed, 46 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index e019db3dc8226..837af136464ba 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -3002,6 +3002,11 @@ static inline int find_acquired_dio_link_enc_for_link( static inline int find_fixed_dio_link_enc(const struct dc_link *link) { + /* virtual links own their link encoder directly and are never + * registered into pool->link_encoders[]. */ + if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) + return -1; + /* the 8b10b dp phy can only use fixed link encoder */ return link->eng_id; } @@ -3147,6 +3152,8 @@ static bool add_dio_link_enc_to_ctx(const struct dc *dc, if (enc_index >= 0) pipe_ctx->link_res.dio_link_enc = pool->link_encoders[enc_index]; + else + pipe_ctx->link_res.dio_link_enc = stream->link->link_enc; return pipe_ctx->link_res.dio_link_enc != NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c index 6cb5e8152cf10..4abf51c8ab52c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c @@ -432,14 +432,24 @@ static bool acquire_aux_engine_without_ddc_pin( struct dce_aux *engine, struct ddc *ddc) { - (void)ddc; if ((engine == NULL) || !is_engine_available(engine)) return false; + /* Open the DDC in AUX mode so the I3C PAD set_config hook runs and + * enables the PAD RX (disabled by default); otherwise DPCD reads time + * out even though the connector has no native I2C/DDC pin. */ + if (ddc != NULL && + dal_ddc_open(ddc, GPIO_MODE_HARDWARE, + GPIO_DDC_CONFIG_TYPE_MODE_AUX) != GPIO_RESULT_OK) + return false; + if (!acquire_engine(engine)) { + engine->ddc = ddc; release_engine(engine); return false; } + + engine->ddc = ddc; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c index b75bfea635fd4..bbfdcfc5b48fe 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c @@ -469,10 +469,11 @@ static enum gpio_result dal_hw_ddc_set_config_i3cpad( switch (config_data->config.ddc.type) { /* For ASICs with i3cpad module there is no dual pad mode for i3cpads */ case GPIO_DDC_CONFIG_TYPE_MODE_I2C: - /* Enable the RX for the PAD (it is disabled by default). */ - REG_UPDATE(dc_i3cpad_control1, DC_I3CPAD_RXSEL, 0); - return GPIO_RESULT_OK; case GPIO_DDC_CONFIG_TYPE_MODE_AUX: + /* Enable the RX for the PAD (it is disabled by default). Required for + * both I2C (EDID) and AUX (DPCD); without it the sink reply is never + * received and the transaction times out. */ + REG_UPDATE(dc_i3cpad_control1, DC_I3CPAD_RXSEL, 0); return GPIO_RESULT_OK; case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT: diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index cb163902e12e7..8c29aa2cd2c92 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -966,6 +966,12 @@ enum dc_status dcn30_setup_hdmi_frl_link( frl_phy_clock_source_id, link->frl_link_settings.frl_link_rate); link->phy_state.symclk_state = SYMCLK_ON_TX_ON; + + /* Enable HPO link encoder */ + link->hpo_frl_link_enc->funcs->setup_link_encoder( + link->hpo_frl_link_enc, + link->frl_link_settings.frl_num_lanes); + return status; } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 42b2fbb8a4ae4..bdefe699f8ca2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1847,7 +1847,10 @@ void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, } if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) { - if (link->link_status.link_active && link->frl_link_settings.frl_link_rate != 0) + bool unblank_required = + link->link_status.link_active && link->frl_link_settings.frl_link_rate != 0; + + if (unblank_required) pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_unblank( pipe_ctx->stream_res.hpo_frl_stream_enc, pipe_ctx->stream_res.tg->inst); diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c index 04df75114dd5b..8110481234012 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c @@ -117,16 +117,18 @@ void enable_hpo_dp_link_output(struct dc_link *link, return; } - if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) - link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( - link->dc->res_pool->dccg, - link_res->hpo_dp_link_enc->inst, - true); - link_res->hpo_dp_link_enc->funcs->enable_link_phy( - link_res->hpo_dp_link_enc, - link_settings, - link->link_enc->transmitter, - link->link_enc->hpd_source); + { + if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) + link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( + link->dc->res_pool->dccg, + link_res->hpo_dp_link_enc->inst, + true); + link_res->hpo_dp_link_enc->funcs->enable_link_phy( + link_res->hpo_dp_link_enc, + link_settings, + link->link_enc->transmitter, + link->link_enc->hpd_source); + } } void disable_hpo_dp_link_output(struct dc_link *link, @@ -231,4 +233,3 @@ const struct link_hwss *get_hpo_dp_link_hwss(void) { return &hpo_dp_link_hwss; } - diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 24e3bbec15ffb..ad1a499b0d9d2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -997,7 +997,8 @@ bool link_decide_link_settings(struct dc_stream_state *stream, * TODO: add MST specific link training routine */ decide_mst_link_settings(link, link_setting); - } else if (stream->signal == SIGNAL_TYPE_VIRTUAL) { + } else if (dc_is_virtual_signal(stream->signal)) { + /* virtual signals skip link training; use a valid dummy setting. */ link_setting->lane_count = LANE_COUNT_FOUR; link_setting->link_rate = LINK_RATE_HIGH3; } else if (link->connector_signal == SIGNAL_TYPE_EDP) { -- 2.43.0
