From: Dillon Varone <[email protected]> [WHY&HOW] For cases where number of OPP/DPP mismatch, like 4 planes, 1 stream on a 3 OPP ASIC, mode support would previously fail citing lack of OPP's. This is incorrect, as the configuration only needs 1 OPP but 4 DPP's.
Reviewed-by: Austin Zheng <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> --- .../dml21/inc/bounding_boxes/dcn42b_soc_bb.h | 10 +++---- .../src/dml2_core/dml2_core_dcn4_calcs.c | 30 ++++++++++--------- .../dml2_core_dcn5_funcs_initialize.c | 2 +- .../dml2_core_dcn5_funcs_mode_support.c | 23 ++++++++++++-- .../dml2_core_dcn6_funcs_initialize.c | 2 ++ .../dml2_core_dcn6_funcs_mode_support.c | 24 +++++++++++++-- 6 files changed, 67 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h index 33eb583e3365e..0f8666788bbb8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42b_soc_bb.h @@ -57,7 +57,6 @@ static const struct dml2_soc_qos_parameters dml_dcn42b_variant_a_soc_qos_params }, .qos_params = { .dcn32x = { - .loaded_round_trip_latency_fclk_cycles = 106, .urgent_latency_us = { .base_latency_us = 4, .base_latency_pixel_vm_us = 4, @@ -65,8 +64,9 @@ static const struct dml2_soc_qos_parameters dml_dcn42b_variant_a_soc_qos_params .scaling_factor_fclk_us = 0, .scaling_factor_mhz = 0, }, - .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, + .loaded_round_trip_latency_fclk_cycles = 106, .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, }, }, @@ -167,7 +167,6 @@ static const struct dml2_soc_bb dml2_socbb_dcn42b = { }, .qos_params = { .dcn32x = { - .loaded_round_trip_latency_fclk_cycles = 106, .urgent_latency_us = { .base_latency_us = 4, .base_latency_pixel_vm_us = 4, @@ -175,8 +174,9 @@ static const struct dml2_soc_bb dml2_socbb_dcn42b = { .scaling_factor_fclk_us = 0, .scaling_factor_mhz = 0, }, - .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, + .loaded_round_trip_latency_fclk_cycles = 106, .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, }, }, @@ -208,8 +208,8 @@ static const struct dml2_soc_bb dml2_socbb_dcn42b = { .return_bus_width_bytes = 64, .hostvm_min_page_size_kbytes = 4, .gpuvm_min_page_size_kbytes = 4, - .gpuvm_max_page_table_levels = 1, .hostvm_max_non_cached_page_table_levels = 2, + .gpuvm_max_page_table_levels = 1, .phy_downspread_percent = 0.38, .dcn_downspread_percent = 0.38, .dispclk_dppclk_vco_speed_mhz = 3000, diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index 9a205b0e15989..608bbb7287cb0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -4116,9 +4116,7 @@ static bool ValidateODMMode(enum dml2_odm_mode ODMMode, bool UseDSC, unsigned int NumberOfDSCSlices, unsigned int TotalNumberOfActiveDPP, - unsigned int TotalNumberOfActiveOPP, unsigned int MaxNumDPP, - unsigned int MaxNumOPP, double DISPCLKRequired, unsigned int NumberOfDPPRequired, unsigned int MaxHActiveForDSC, @@ -4134,7 +4132,7 @@ static bool ValidateODMMode(enum dml2_odm_mode ODMMode, if (DISPCLKRequired > MaxDispclk) return false; - if ((TotalNumberOfActiveDPP + NumberOfDPPRequired) > MaxNumDPP || (TotalNumberOfActiveOPP + NumberOfDPPRequired) > MaxNumOPP) + if ((TotalNumberOfActiveDPP + NumberOfDPPRequired) > MaxNumDPP) return false; if (are_odm_segments_symmetrical) { if (HActive % (NumberOfDPPRequired * pixels_per_clock_cycle)) @@ -4180,9 +4178,7 @@ static noinline_for_stack void CalculateODMMode( double MaxDispclk, bool DSCEnable, unsigned int TotalNumberOfActiveDPP, - unsigned int TotalNumberOfActiveOPP, unsigned int MaxNumDPP, - unsigned int MaxNumOPP, double PixelClock, unsigned int NumberOfDSCSlices, @@ -4252,9 +4248,7 @@ static noinline_for_stack void CalculateODMMode( UseDSC, NumberOfDSCSlices, TotalNumberOfActiveDPP, - TotalNumberOfActiveOPP, MaxNumDPP, - MaxNumOPP, DISPCLKRequired, NumberOfDPPRequired, MaxHActiveForDSC, @@ -8453,7 +8447,6 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out CalculateSwathAndDETConfiguration(&mode_lib->scratch, CalculateSwathAndDETConfiguration_params); mode_lib->ms.TotalNumberOfActiveDPP = 0; - mode_lib->ms.TotalNumberOfActiveOPP = 0; mode_lib->ms.support.TotalAvailablePipesSupport = true; for (k = 0; k < mode_lib->ms.num_active_planes; ++k) { @@ -8489,9 +8482,7 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.max_dispclk_freq_mhz, false, // DSCEnable mode_lib->ms.TotalNumberOfActiveDPP, - mode_lib->ms.TotalNumberOfActiveOPP, mode_lib->ip.max_num_dpp, - mode_lib->ip.max_num_opp, ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000), mode_lib->ms.support.NumberOfDSCSlices[k], @@ -8510,9 +8501,7 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.max_dispclk_freq_mhz, true, // DSCEnable mode_lib->ms.TotalNumberOfActiveDPP, - mode_lib->ms.TotalNumberOfActiveOPP, mode_lib->ip.max_num_dpp, - mode_lib->ip.max_num_opp, ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000), mode_lib->ms.support.NumberOfDSCSlices[k], @@ -8650,12 +8639,25 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out #endif } + // TotalNumberOfActiveDPP is the sum of all planes mode_lib->ms.TotalNumberOfActiveDPP = 0; - mode_lib->ms.TotalNumberOfActiveOPP = 0; for (k = 0; k < mode_lib->ms.num_active_planes; ++k) { mode_lib->ms.TotalNumberOfActiveDPP += mode_lib->ms.NoOfDPP[k]; - mode_lib->ms.TotalNumberOfActiveOPP += mode_lib->ms.NoOfOPP[k]; } + + // TotalNumberOfActiveOPP is the sum of the per stream max of all planes + mode_lib->ms.TotalNumberOfActiveOPP = 0; + for (k = 0; k < display_cfg->num_streams; ++k) { + unsigned int NoOfOppPerStream = 0; + for (m = 0; m < display_cfg->num_planes; ++m) { + if (display_cfg->plane_descriptors[m].stream_index == k) { + NoOfOppPerStream = NoOfOppPerStream < mode_lib->ms.NoOfOPP[m] ? mode_lib->ms.NoOfOPP[m] : NoOfOppPerStream; + } + } + + mode_lib->ms.TotalNumberOfActiveOPP += NoOfOppPerStream; + } + if (mode_lib->ms.TotalNumberOfActiveDPP > (unsigned int)mode_lib->ip.max_num_dpp) mode_lib->ms.support.TotalAvailablePipesSupport = false; if (mode_lib->ms.TotalNumberOfActiveOPP > (unsigned int)mode_lib->ip.max_num_opp) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_initialize.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_initialize.c index 31681c7f655e9..5907cc155505a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_initialize.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_initialize.c @@ -33,7 +33,7 @@ static void patch_ip_caps_with_explicit_ip_params(struct dml2_ip_capabilities *i static void patch_ip_params_with_ip_caps(struct dml2_core_ip_params *ip_params, const struct dml2_ip_capabilities *ip_caps) { ip_params->max_num_dpp = ip_caps->pipe_count; - ip_params->max_num_opp = ip_caps->pipe_count; + ip_params->max_num_opp = ip_caps->otg_count; ip_params->max_num_otg = ip_caps->otg_count; ip_params->num_dsc = ip_caps->num_dsc; ip_params->max_num_dp2p0_streams = ip_caps->max_num_dp2p0_streams; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_support.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_support.c index 9d68c9dd0a1de..2e86a134e074e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_support.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_support.c @@ -795,22 +795,26 @@ static void dcn5_ms_calculate_num_of_dpp_required( const struct dml2_display_cfg *display_cfg, struct dml2_core_internal_display_mode_lib *mode_lib) { - unsigned int k; + unsigned int k, m; const struct dml2_plane_parameters *plane; for (k = 0; k < mode_lib->ms.num_active_planes; ++k) { plane = &display_cfg->plane_descriptors[k]; mode_lib->ms.MPCCombine[k] = false; mode_lib->ms.NoOfDPP[k] = 1; + mode_lib->ms.NoOfOPP[k] = 1; if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1) { mode_lib->ms.MPCCombine[k] = false; mode_lib->ms.NoOfDPP[k] = 4; + mode_lib->ms.NoOfOPP[k] = 4; } else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1) { mode_lib->ms.MPCCombine[k] = false; mode_lib->ms.NoOfDPP[k] = 3; + mode_lib->ms.NoOfOPP[k] = 3; } else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1) { mode_lib->ms.MPCCombine[k] = false; mode_lib->ms.NoOfDPP[k] = 2; + mode_lib->ms.NoOfOPP[k] = 2; } else if (plane->overrides.mpcc_combine_factor == 2) { mode_lib->ms.MPCCombine[k] = true; mode_lib->ms.NoOfDPP[k] = 2; @@ -832,12 +836,27 @@ static void dcn5_ms_calculate_num_of_dpp_required( DML_LOG_VERBOSE("DML::%s: k=%d, NoOfDPP = %d\n", __func__, k, mode_lib->ms.NoOfDPP[k]); } + + + // TotalNumberOfActiveOPP is the sum of the per stream max NoOfOPP of all planes driving that stream + mode_lib->ms.TotalNumberOfActiveOPP = 0; + for (k = 0; k < display_cfg->num_streams; ++k) { + unsigned int NoOfOppPerStream = 0; + + for (m = 0; m < mode_lib->ms.num_active_planes; ++m) { + if (display_cfg->plane_descriptors[m].stream_index == k) + NoOfOppPerStream = NoOfOppPerStream < mode_lib->ms.NoOfOPP[m] ? mode_lib->ms.NoOfOPP[m] : NoOfOppPerStream; + } + + mode_lib->ms.TotalNumberOfActiveOPP += NoOfOppPerStream; + } } static bool dcn5_ms_check_total_available_pipes_support( struct dml2_core_internal_display_mode_lib *mode_lib) { - return mode_lib->ms.TotalNumberOfActiveDPP <= (unsigned int) mode_lib->ip.max_num_dpp; + return mode_lib->ms.TotalNumberOfActiveDPP <= (unsigned int) mode_lib->ip.max_num_dpp + && mode_lib->ms.TotalNumberOfActiveOPP <= (unsigned int) mode_lib->ip.max_num_opp; } static void dcn5_ms_calculate_total_num_of_single_dpp_surfaces( diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_initialize.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_initialize.c index 23fd6edeb0cf2..5abce647da0a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_initialize.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_initialize.c @@ -24,6 +24,7 @@ struct dml2_core_ip_params core_dcn6_ip_caps_base = { .writeback_interface_buffer_size_kbytes = 90, //Number of pipes after DCN Pipe harvesting .max_num_dpp = 4, + .max_num_opp = 4, .max_num_otg = 4, .max_num_wb = 1, .zero_size_buffer_entries = 512, @@ -111,6 +112,7 @@ static void patch_ip_caps_with_explicit_ip_params(struct dml2_ip_capabilities *i static void patch_ip_params_with_ip_caps(struct dml2_core_ip_params *ip_params, const struct dml2_ip_capabilities *ip_caps) { ip_params->max_num_dpp = ip_caps->pipe_count; + ip_params->max_num_opp = ip_caps->otg_count; ip_params->max_num_otg = ip_caps->otg_count; ip_params->TDLUT_33cube_count = ip_caps->TDLUT_33cube_count; ip_params->num_dsc = ip_caps->num_dsc; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c index 01bbf4aacbe3c..ca3b8b82ec04a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c @@ -988,12 +988,16 @@ static void dcn6_ms_calculate_num_of_dpp_required( for (k = 0; k < display_cfg->num_planes; k++) { plane = &display_cfg->plane_descriptors[k]; outputs->NoOfDPP[k] = 1; + outputs->NoOfOPP[k] = 1; if (inputs->ODMMode[k] == dml2_odm_mode_combine_4to1) { outputs->NoOfDPP[k] = 4; + outputs->NoOfOPP[k] = 4; } else if (inputs->ODMMode[k] == dml2_odm_mode_combine_3to1) { outputs->NoOfDPP[k] = 3; + outputs->NoOfOPP[k] = 3; } else if (inputs->ODMMode[k] == dml2_odm_mode_combine_2to1) { outputs->NoOfDPP[k] = 2; + outputs->NoOfOPP[k] = 2; } else if (plane->overrides.mpcc_combine_factor == 2) { outputs->MPCCombine[k] = true; outputs->NoOfDPP[k] = 2; @@ -1027,12 +1031,28 @@ static bool dcn6_ms_check_total_available_pipes_support( struct dml2_core_internal_mode_support *inputs = states; struct dml2_core_internal_mode_support *outputs = states; unsigned int totalNumOfActiveDPP = 0; - unsigned int k; + unsigned int k, m; DML_LOG_FUNC_ENTER(); for (k = 0; k < display_cfg->num_planes; k++) totalNumOfActiveDPP += inputs->NoOfDPP[k]; - outputs->support.TotalAvailablePipesSupport = totalNumOfActiveDPP <= (unsigned int)ip->max_num_dpp; + + + // TotalNumberOfActiveOPP is the sum of the per stream max NoOfOPP of all planes driving that stream + outputs->TotalNumberOfActiveOPP = 0; + for (k = 0; k < display_cfg->num_streams; k++) { + unsigned int NoOfOppPerStream = 0; + + for (m = 0; m < display_cfg->num_planes; m++) { + if (display_cfg->plane_descriptors[m].stream_index == k) + NoOfOppPerStream = NoOfOppPerStream < inputs->NoOfOPP[m] ? inputs->NoOfOPP[m] : NoOfOppPerStream; + } + + outputs->TotalNumberOfActiveOPP += NoOfOppPerStream; + } + + outputs->support.TotalAvailablePipesSupport = totalNumOfActiveDPP <= (unsigned int)ip->max_num_dpp + && outputs->TotalNumberOfActiveOPP <= (unsigned int)ip->max_num_opp; DML_LOG_DEBUG_BOOL(outputs->support.TotalAvailablePipesSupport); DML_LOG_FUNC_EXIT(); -- 2.43.0
