Add the GFX case to the mqd_update dispatcher so a GFX user queue can be updated at runtime; until now it was rejected with -EINVAL.
mes_userq_gfx_mqd_update() reads a drm_amdgpu_userq_mqd_gfx11 from user space, refreshes the queue props (shadow address, csa address, queue size and ring base) and re-inits the MQD, mirroring the compute and SDMA paths. Suggested-by: Alexander Deucher <[email protected]> Signed-off-by: Jesse Zhang <[email protected]> --- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 4f6d92031838..6b5095efdfc5 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -711,6 +711,37 @@ static int mes_userq_sdma_mqd_update(struct amdgpu_usermode_queue *queue, return retval; } +static int mes_userq_gfx_mqd_update(struct amdgpu_usermode_queue *queue, + struct drm_amdgpu_userq_in *args_in) +{ + int retval = 0; + struct amdgpu_device *adev = queue->userq_mgr->adev; + struct amdgpu_mqd_prop *userq_props = queue->userq_prop; + struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; + struct drm_amdgpu_userq_mqd_gfx11 *gfx_mqd_v11; + + if (args_in->mqd_size != sizeof(*gfx_mqd_v11)) { + DRM_ERROR("Invalid GFX IP MQD size\n"); + return -EINVAL; + } + + gfx_mqd_v11 = memdup_user(u64_to_user_ptr(args_in->mqd), args_in->mqd_size); + if (IS_ERR(gfx_mqd_v11)) { + DRM_ERROR("Failed to read user MQD\n"); + return -ENOMEM; + } + + userq_props->shadow_addr = gfx_mqd_v11->shadow_va; + userq_props->csa_addr = gfx_mqd_v11->csa_va; + userq_props->queue_size = args_in->queue_size; + userq_props->hqd_base_gpu_addr = args_in->queue_va; + + retval = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); + + kfree(gfx_mqd_v11); + return retval; +} + static int mes_userq_compute_mqd_update(struct amdgpu_usermode_queue *queue, struct drm_amdgpu_userq_in *args_in) { @@ -753,6 +784,8 @@ static int mes_userq_mqd_update(struct amdgpu_usermode_queue *queue, struct drm_ switch (queue->queue_type) { case AMDGPU_HW_IP_COMPUTE: return mes_userq_compute_mqd_update(queue, args_in); + case AMDGPU_HW_IP_GFX: + return mes_userq_gfx_mqd_update(queue, args_in); case AMDGPU_HW_IP_DMA: return mes_userq_sdma_mqd_update(queue, args_in); default: -- 2.49.0
