AMD General Patch # 1 ~ 2 are Reviewed-by: Hawking Zhang <[email protected]>
Patch #3 is not needed. Regards, Hawking -----Original Message----- From: amd-gfx <[email protected]> On Behalf Of Xiang Liu Sent: Thursday, August 20, 2026 10:05 PM To: [email protected] Cc: Zhang, Hawking <[email protected]>; Zhou1, Tao <[email protected]>; Yang, Stanley <[email protected]>; Chai, Thomas <[email protected]>; Liu, Xiang(Dean) <[email protected]> Subject: [PATCH 3/3] drm/amd/ras: keep reporting the socket id in the RAS feature mask The socket id of a device is exported through the ras "features" sysfs node, where con->features carries it in bits[31:29]. Reporting the RAS capability mask there instead changes that layout: it spends bits[55:0] on block bits and so carries the socket id in bits[62:60]. Tools that decode bits[31:29] then read block capability bits, which are identical on every device of a hive. XGMI error injection depends on this. The tool resolves a WAFL sub block to its destination socket, looks up the device carrying that socket id and injects there. Once every device claims the same socket id the lookup silently falls back to the first device and to instance mask 0, so the injection lands on the wrong device and the RAS TA rejects it with RAS_TA_STATUS__ERROR_PCS_STATE_HANG. Only report the capability mask on parts whose tools decode the wider layout, and keep reporting con->features on the others. Fixes: 6ae383bdf282 ("drm/amdgpu: Support obtaining ras capabilities") Signed-off-by: Xiang Liu <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index d168e5d54d87..0dec6da3f1d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1845,10 +1845,19 @@ static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, { struct amdgpu_ras *con = container_of(attr, struct amdgpu_ras, features_attr); + struct amdgpu_device *adev = con->adev; u64 ras_features; - ras_features = amdgpu_uniras_enabled(con->adev) ? - amdgpu_uniras_get_ras_caps(con->adev) : con->features; + /* The wide capability mask needs bits[31:29] for block bits and so + * reports the socket id in bits[62:60] instead. Only newer parts may + * use it: on older ones tools still decode bits[31:29], and without a + * socket id there they cannot tell the devices of a hive apart. + */ + if (amdgpu_uniras_enabled(adev) && + amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0)) + ras_features = amdgpu_uniras_get_ras_caps(adev); + else + ras_features = con->features; return sysfs_emit(buf, "feature mask: 0x%llx\n", ras_features); } -- 2.34.1
