AMD General Please update the inline comments when you commit the patch. Thank you
Reviewed-by: Hawking Zhang <[email protected]> Regards, Hawking -----Original Message----- From: amd-gfx <[email protected]> On Behalf Of Xiang Liu Sent: Friday, August 21, 2026 11:44 AM To: [email protected] Cc: Zhang, Hawking <[email protected]>; Zhou1, Tao <[email protected]>; Yang, Stanley <[email protected]>; Chai, Thomas <[email protected]>; Liu, Xiang(Dean) <[email protected]> Subject: [PATCH] drm/amd/ras: keep the established socket id layout on older parts The socket id is exported through the ras "features" sysfs node in bits[31:29] of a 32 bit mask, but the RAS capability mask is 64 bit and reports it in bits[62:60]. Tools parsing the node into a 32 bit variable read block capability bits instead, which are identical across a hive, so XGMI injection resolves every WAFL sub block to the first device and the RAS TA rejects it with RAS_TA_STATUS__ERROR_PCS_STATE_HANG. Keep building the 32 bit layout from the same capability mask on parts released before the 64 bit one, and stop assigning the multi bit adev->ras_enabled to the single bit en field. Fixes: 6ae383bdf282 ("drm/amdgpu: Support obtaining ras capabilities") Signed-off-by: Xiang Liu <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index d168e5d54d87..34de9daa6124 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -5065,16 +5065,27 @@ uint64_t amdgpu_uniras_get_ras_caps(struct amdgpu_device *adev) struct ras_cmd_get_ras_cap_req req = {0}; struct ras_cmd_get_ras_cap_rsp rsp = {0}; union ras_feature feature = {0}; + u32 socket_id = 0; if (amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__GET_RAS_CAP, &req, sizeof(struct ras_cmd_get_ras_cap_req), &rsp, sizeof(struct ras_cmd_get_ras_cap_rsp))) return 0; - feature.block_mask = rsp.ras_block_mask; - feature.en = adev->ras_enabled; if (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) - feature.tag = adev->smuio.funcs->get_socket_id(adev); + socket_id = adev->smuio.funcs->get_socket_id(adev); + + /* The wide layout spends bits[55:0] on block bits and so relocates the + * socket id. Older parts have to keep the 32 bit one every tool in the + * field parses today, socket id in bits[31:29] included. + */ + if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 1, 0)) + return AMDGPU_RAS_GET_FEATURES(lower_32_bits(rsp.ras_block_mask)) | + (socket_id << AMDGPU_RAS_FEATURES_SOCKETID_SHIFT); + + feature.block_mask = rsp.ras_block_mask; + feature.en = !!adev->ras_enabled; + feature.tag = socket_id; return feature.value; } -- 2.34.1
