From: Dillon Varone <[email protected]> [WHY&HOW] Not all ASIC revisions support the DAL port idle optimizations. Guard the code with a check for ASIC rev.
Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Hung <[email protected]> --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c index 218856c5fe09..c6f90b90c10b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c @@ -1539,6 +1539,9 @@ static void dcn60_set_idle_power_optimizations(struct clk_mgr *clk_mgr_base, boo if (!clk_mgr->smu_present) return; + if (!ASICREV_IS_DCN6_VARIANT_LITE3(clk_mgr_base->ctx->asic_id.hw_internal_rev)) + return; + dcn60_smu_set_display_idle_optimization(clk_mgr, enable); } -- 2.43.0
