From: Mukul Joshi <[email protected]> Map NPA addresses into importer's application page tables using a unique pairing of PTE fields.
Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- .../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++- drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c | 30 +++++++++++++++++-- 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h index 8908d9e08a304..6650b1194c0f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h @@ -92,6 +92,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res, case TTM_PL_TT: case AMDGPU_PL_DOORBELL: case AMDGPU_PL_MMIO_REMAP: + case AMDGPU_PL_NPA: node = to_ttm_range_mgr_node(res)->mm_nodes; while (start >= node->size << PAGE_SHIFT) start -= node++->size << PAGE_SHIFT; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 4c8341b4fe1bc..fc928c2d8b21e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1196,7 +1196,9 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, uint64_t tmp, num_entries, addr; num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT; - if (pages_addr) { + if (res && res->mem_type == AMDGPU_PL_NPA) { + addr = cursor.start; + } else if (pages_addr) { bool contiguous = true; if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c index a8e32ee93735d..1468047687652 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -600,6 +600,21 @@ static void gmc_v12_1_get_vm_pde(struct amdgpu_device *adev, int level, } } +static void gmc_v12_1_get_npa_flags(struct amdgpu_device *adev, + uint64_t *flags) +{ + bool is_aid_a1 = (adev->rev_id & 0x10); + unsigned int mtype_remote; + + mtype_remote = is_aid_a1 ? MTYPE_NC : MTYPE_UC; + + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, mtype_remote); + /* VSCT = 0011 to identify NPA. Additionally PTE.B = 1 */ + *flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT_GFX12 | + AMDGPU_PTE_BUS_ATOMICS; + *flags &= ~AMDGPU_PTE_VALID; +} + static void gmc_v12_1_get_coherence_flags(struct amdgpu_device *adev, struct amdgpu_bo *bo, uint64_t *flags) @@ -668,6 +683,8 @@ static void gmc_v12_1_get_vm_pte(struct amdgpu_device *adev, uint32_t vm_flags, uint64_t *flags) { + struct ttm_resource *mem; + if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) *flags |= AMDGPU_PTE_EXECUTABLE; else @@ -689,8 +706,17 @@ static void gmc_v12_1_get_vm_pte(struct amdgpu_device *adev, break; } - if ((*flags & AMDGPU_PTE_VALID) && bo) - gmc_v12_1_get_coherence_flags(adev, bo, flags); + if (bo) { + mem = bo->tbo.resource; + if (mem && mem->mem_type == AMDGPU_PL_NPA) { + dev_dbg(adev->dev, + "Setting PTE for NPA BO, mem->type: %d, mem->start: %lx, mem->size: %u, cur_flags: %llx\n", + mem->mem_type, mem->start, (u32)mem->size, *flags); + gmc_v12_1_get_npa_flags(adev, flags); + } else if (*flags & AMDGPU_PTE_VALID) { + gmc_v12_1_get_coherence_flags(adev, bo, flags); + } + } } static const struct amdgpu_gmc_funcs gmc_v12_1_gmc_funcs = { -- 2.55.0
