On 9/1/26 11:51, Arunpravin Paneer Selvam wrote:
> Clear-on-release only runs on VRAM, which amdgpu_ttm_map_buffer() reaches
> via its direct MC address without programming a GART window, yet the wipe
> still forces a VMID 0 flush. On GFX11 (e.g. Navi33) that spurious SDMA
> flush can wedge the engine; only flush when a GART window is actually used.
>
> v2: Let amdgpu_ttm_map_buffer() return whether the VMID 0 flush is needed,
> and drive the clear and copy paths from that. (Christian)
> v3: Make the vm_needs_flush output parameter mandatory instead of
> allowing NULL. (Christian)
>
> Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality")
> Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5413
> Cc: [email protected]
> Cc: Christian König <[email protected]>
> Signed-off-by: Arunpravin Paneer Selvam <[email protected]>
> Reviewed-by: Timur Kristóf <[email protected]>
Reviewed-by: Christian König <[email protected]>
Any news on the HW bug? If not please ping people again or we need to escalate
this.
Thanks,
Christian.
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20 ++++++++++++++------
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 6c07cee8e8777..bddecdd64f084 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -190,6 +190,8 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct
> amdgpu_ttm_buffer_entit
> * @tmz: if we should setup a TMZ enabled mapping
> * @size: in number of bytes to map, out number of bytes mapped
> * @addr: resulting address inside the MC address space
> + * @vm_needs_flush: out, set true if a GART window was programmed (VMID 0
> flush
> + * needed) or false for a direct address
> *
> * Setup one of the GART windows to access a specific piece of memory or
> return
> * the physical address for local memory.
> @@ -199,7 +201,8 @@ static int amdgpu_ttm_map_buffer(struct
> amdgpu_ttm_buffer_entity *entity,
> struct ttm_resource *mem,
> struct amdgpu_res_cursor *mm_cur,
> unsigned int window,
> - bool tmz, uint64_t *size, uint64_t *addr)
> + bool tmz, uint64_t *size, uint64_t *addr,
> + bool *vm_needs_flush)
> {
> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
> unsigned int offset, num_pages, num_dw, num_bytes;
> @@ -220,9 +223,12 @@ static int amdgpu_ttm_map_buffer(struct
> amdgpu_ttm_buffer_entity *entity,
> if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
> *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
> mm_cur->start;
> + *vm_needs_flush = false;
> return 0;
> }
>
> + /* A GART window is programmed below, so its VMID 0 TLB needs a flush */
> + *vm_needs_flush = true;
>
> /*
> * If start begins at an offset inside the page, then adjust the size
> @@ -322,6 +328,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct
> amdgpu_device *adev,
> while (src_mm.remaining) {
> uint64_t from, to, cur_size, tiling_flags;
> uint32_t num_type, data_format, max_com, write_compress_disable;
> + bool src_vm_flush, dst_vm_flush;
> struct dma_fence *next;
>
> /* Never copy more than 256MiB at once to avoid a timeout */
> @@ -329,12 +336,12 @@ static int amdgpu_ttm_copy_mem_to_mem(struct
> amdgpu_device *adev,
>
> /* Map src to window 0 and dst to window 1. */
> r = amdgpu_ttm_map_buffer(entity, src->bo, src->mem, &src_mm,
> - 0, tmz, &cur_size, &from);
> + 0, tmz, &cur_size, &from,
> &src_vm_flush);
> if (r)
> goto error;
>
> r = amdgpu_ttm_map_buffer(entity, dst->bo, dst->mem, &dst_mm,
> - 1, tmz, &cur_size, &to);
> + 1, tmz, &cur_size, &to,
> &dst_vm_flush);
> if (r)
> goto error;
>
> @@ -362,7 +369,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct
> amdgpu_device *adev,
> }
>
> r = amdgpu_copy_buffer(adev, entity, from, to, cur_size, resv,
> - &next, true, copy_flags);
> + &next, src_vm_flush || dst_vm_flush,
> copy_flags);
> if (r)
> goto error;
>
> @@ -2578,6 +2585,7 @@ int amdgpu_ttm_clear_buffer(struct
> amdgpu_ttm_buffer_entity *entity,
> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> struct dma_fence *fence = NULL;
> struct amdgpu_res_cursor dst;
> + bool vm_needs_flush = false;
> int r;
>
> if (!entity)
> @@ -2599,13 +2607,13 @@ int amdgpu_ttm_clear_buffer(struct
> amdgpu_ttm_buffer_entity *entity,
> cur_size = min(dst.size, 256ULL << 20);
>
> r = amdgpu_ttm_map_buffer(entity, &bo->tbo, bo->tbo.resource,
> &dst,
> - 0, false, &cur_size, &to);
> + 0, false, &cur_size, &to,
> &vm_needs_flush);
> if (r)
> goto error;
>
> r = amdgpu_ttm_fill_mem(adev, entity,
> 0, to, cur_size, resv,
> - &next, true, k_job_id);
> + &next, vm_needs_flush, k_job_id);
> if (r)
> goto error;
>
