When the driver is loaded on a device that still needs a hive reset, the RAS IP hw_init is deferred to amdgpu_ras_mgr_resume_after_reset(). The MCA configuration is sent to PMFW from amdgpu_ras_late_init(), which runs during the reset while RAS is not ready yet, so the request is dropped and CE polling stays disabled. Correctable errors are then never harvested and only show up on the next driver load.
Re-apply the current debug mode once hw_init has completed. Signed-off-by: Xiang Liu <[email protected]> --- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index a02167397ce2..f550e83f2b96 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -483,6 +483,7 @@ int amdgpu_ras_mgr_resume_after_reset(struct amdgpu_device *adev) struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); struct amdgpu_ip_block *ip_block; + int ret; if (!con || !con->uniras_enabled) return 0; @@ -497,7 +498,12 @@ int amdgpu_ras_mgr_resume_after_reset(struct amdgpu_device *adev) if (!ip_block) return -EINVAL; - return amdgpu_ras_mgr_hw_init(ip_block); + ret = amdgpu_ras_mgr_hw_init(ip_block); + if (ret) + return ret; + + /* amdgpu_ras_late_init() runs before RAS is ready on this path */ + return amdgpu_ras_mgr_set_debug_mode(adev, ras_mgr->is_debug_mode); } struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context(struct amdgpu_device *adev) -- 2.34.1
