AMD General
Hi Xiang, Ce:
After gpu reset, the amdgpu_ras_mgr_post_reset also will be
called, if calling amdgpu_ras_mgr_set_debug_mode in this function, can it cover
all requirements?
Best Regards,
Thomas
From: Liu, Xiang(Dean) <[email protected]>
Sent: Sunday, September 6, 2026 5:10 PM
To: Sun, Ce(Overlord) <[email protected]>; Zhang, Hawking <[email protected]>;
[email protected]
Cc: Zhou1, Tao <[email protected]>; Yang, Stanley <[email protected]>; Chai,
Thomas <[email protected]>
Subject: Re: [PATCH 1/3] drm/amd/ras: reprogram MCA settings after reset
AMD General
Hi Hawking, Ce,
Both changes look good to me. I think we need one more call to cover the normal
GPU reset though.
amdgpu_ip_block_resume() calls .resume and never falls back to .hw_init, and
the RAS block registers both:
.hw_init = amdgpu_ras_mgr_hw_init,
.resume = amdgpu_ras_mgr_resume,
hw_init does not run on an ordinary reset. ras_is_ready also stays true across
it - it is cleared only in hw_fini, which the reset path does not call, and
.suspend is a no-op - so resume_after_reset() returns early as well. Once the
call is gone from late_init, nothing reprograms MCA on that path.
So on top of 1 and 2, adding it to amdgpu_ras_mgr_resume() after the
!ras_is_ready guard.
That also answers Ce: the UE injection reset comes back through .resume, so the
mode is reprogrammed before the next CE injection.
Best Regards,
Liu, Xiang
________________________________
From: Sun, Ce(Overlord) <[email protected]<mailto:[email protected]>>
Sent: Sunday, September 6, 2026 3:55 PM
To: Zhang, Hawking <[email protected]<mailto:[email protected]>>; Liu,
Xiang(Dean) <[email protected]<mailto:[email protected]>>;
[email protected]<mailto:[email protected]>
<[email protected]<mailto:[email protected]>>
Cc: Zhou1, Tao <[email protected]<mailto:[email protected]>>; Yang, Stanley
<[email protected]<mailto:[email protected]>>; Chai, Thomas
<[email protected]<mailto:[email protected]>>
Subject: Re: [PATCH 1/3] drm/amd/ras: reprogram MCA settings after reset
AMD General
Hi Hawking,
Thanks for proposing this cleaner initialization sequence.
One corner case concern: after we remove amdgpu_ras_mgr_set_debug_mode from
amdgpu_ras_late_init, when we perform UE error injection, set_debug_mode will
not get re‑applied. This may cause failures on subsequent CE error injection
operations.
Do you think we need to handle this scenario additionally?
Regards,
Sun Ce
________________________________
From: Zhang, Hawking <[email protected]<mailto:[email protected]>>
Sent: Saturday, September 5, 2026 4:23 PM
To: Liu, Xiang(Dean) <[email protected]<mailto:[email protected]>>;
[email protected]<mailto:[email protected]>
<[email protected]<mailto:[email protected]>>; Sun,
Ce(Overlord) <[email protected]<mailto:[email protected]>>
Cc: Zhou1, Tao <[email protected]<mailto:[email protected]>>; Yang, Stanley
<[email protected]<mailto:[email protected]>>; Chai, Thomas
<[email protected]<mailto:[email protected]>>
Subject: RE: [PATCH 1/3] drm/amd/ras: reprogram MCA settings after reset
AMD General
+ @Sun, Ce(Overlord)<mailto:[email protected]> for the discussion.
Hey Guys,
We may need a cleaner and more consistent initialization sequence that covers
normal driver initialization/modprobe, regular GPU reset and recovery, and XGMI
reset and recovery.
Could you please evaluate the following changes?
1. Move the call to amdgpu_ras_mgr_set_debug_mode into amdgpu_ras_mgr_hw_init,
placing it as the final initialization step before the marks uniras as enabled.
2. Remove the corresponding amdgpu_ras_mgr_set_debug_mode call and the uniras
enable check from amdgpu_ras_late_init.
Regards,
Hawking
-----Original Message-----
From: Liu, Xiang(Dean) <[email protected]<mailto:[email protected]>>
Sent: Saturday, September 5, 2026 12:30 PM
To: [email protected]<mailto:[email protected]>
Cc: Zhang, Hawking <[email protected]<mailto:[email protected]>>;
Zhou1, Tao <[email protected]<mailto:[email protected]>>; Yang, Stanley
<[email protected]<mailto:[email protected]>>; Chai, Thomas
<[email protected]<mailto:[email protected]>>; Liu, Xiang(Dean)
<[email protected]<mailto:[email protected]>>
Subject: [PATCH 1/3] drm/amd/ras: reprogram MCA settings after reset
When the driver is loaded on a device that still needs a hive reset, the RAS IP
hw_init is deferred to amdgpu_ras_mgr_resume_after_reset().
The MCA configuration is sent to PMFW from amdgpu_ras_late_init(), which runs
during the reset while RAS is not ready yet, so the request is dropped and CE
polling stays disabled. Correctable errors are then never harvested and only
show up on the next driver load.
Re-apply the current debug mode once hw_init has completed.
Signed-off-by: Xiang Liu <[email protected]<mailto:[email protected]>>
---
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
index a02167397ce2..f550e83f2b96 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
@@ -483,6 +483,7 @@ int amdgpu_ras_mgr_resume_after_reset(struct amdgpu_device
*adev)
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
struct amdgpu_ip_block *ip_block;
+ int ret;
if (!con || !con->uniras_enabled)
return 0;
@@ -497,7 +498,12 @@ int amdgpu_ras_mgr_resume_after_reset(struct amdgpu_device
*adev)
if (!ip_block)
return -EINVAL;
- return amdgpu_ras_mgr_hw_init(ip_block);
+ ret = amdgpu_ras_mgr_hw_init(ip_block);
+ if (ret)
+ return ret;
+
+ /* amdgpu_ras_late_init() runs before RAS is ready on this path */
+ return amdgpu_ras_mgr_set_debug_mode(adev, ras_mgr->is_debug_mode);
}
struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context(struct amdgpu_device *adev)
--
2.34.1
