Hi Kenneth, hi Atharva,
Thanks for bringing the two threads together. I've tried your suggestion on
my iMac20,1 (1002:7340 / 106b:0218, revision 0x41), with SMU firmware
53.38.0. Two warm boots both failed.
On the same AMD staging base as my RFC, I moved UCLK enablement to the
beginning of navi10_set_default_dpm_table(), along with the readback check
and supported-feature update. I removed the later enable and refresh from
post-init. UCLK was still excluded from enable-all, and both memory-voltage
features stayed the same. I didn't add any delay or extra mailbox tracing.
Both boots reported:
SMU: No response msg_reg: 8 resp_reg: 0
in params:00000008
Apple 0218 default-table UCLK enable failed: -62
AMDGPU failed to bind in both cases. I checked that the experimental module
was loaded and the firmware files hadn't changed.
This also fits an earlier test with T2 7.1.8. With UCLK excluded from
enable-all, I tried enabling it separately immediately after
smu_v11_0_system_features_control(smu, true) returned successfully. The
trace shows EnableAllSmuFeatures returning 0x1, then EnableSmuFeaturesLow
with argument 0x8 timing out with response 0 and -ETIME.
The default-table function is reached only after enable-all returns
successfully, so waiting for that acknowledgement doesn't seem to be enough
on this board. I don't yet know whether it needs more time or some other
initialization step. I'd keep post-init for now: that version passed the
ten recorded AMD staging warm boots. These tests don't establish the
earliest safe point.
As for Apple, I can't speak for Apple or confirm their approval. I'm
testing this as a Linux user. Do we need Apple's input before merging an
Apple-specific workaround? If so, could AMD help find the right contact?
I'd still welcome a fix for the underlying firmware problem.
I agree we should coordinate the two patches. Mine covers only 0218/rev
0x41; Atharva's covers 0219. We'd still need to test the combined change on
both boards.
Thanks!
Ed
On 9 Sep 2026 at 5:05:51 pm, "Feng, Kenneth" <[email protected]> wrote:
> AMD General
>
> This issue is also addressed in the thread: [RFC PATCH] drm/amd/pm: defer
> UCLK DPM enablement on Apple Navi 14 0218.
> I think the workaround can be merged for Apple specifically between this
> patch and that patch from Ed Schofield.
> The same questions:
> 1. can this workaround setting be put right after the
> SMU_MSG_EnableAllSmuFeatures is acked?
> 2. Does Apple accept this workaround instead of a root cause on how
> SMU_MSG_EnableAllSmuFeatures is not acked back?
> Thanks.
>
>
> -----Original Message-----
> From: Atharva Tiwari <[email protected]>
> Sent: Tuesday, August 25, 2026 3:04 AM
> Cc: Atharva Tiwari <[email protected]>; Guna R . Bharati <
> [email protected]>; Feng, Kenneth <[email protected]>; Deucher,
> Alexander <[email protected]>; Koenig, Christian <
> [email protected]>; David Airlie <[email protected]>; Simona
> Vetter <[email protected]>; [email protected];
> [email protected]; [email protected]
> Subject: [PATCH] drm/amdgpu/smu: Enable UCLK after init in AMD Radeon Pro
> 5300
>
> [You don't often get email from [email protected]. Learn
> why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On the AMD Radeon PRO 5300, enabling UCLK_BIT in
> navi10_init_allowed_features causes errors such as:
>
> SMU: No response msg_reg: 6 resp_reg: 0
>
> or:
>
> SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x00000006
> SMN_C2PMSG_82:0x00000000
>
> To work around this issue, we use smu_set_pp_feature_mask() to enable
> UCLK_BIT instead.
>
> Fixes:
> https://gitlab.freedesktop.org/drm/amd/-/work_items/4895
>
> Tested-by: Guna R. Bharati <[email protected]>
> Signed-off-by: Atharva Tiwari <[email protected]>
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 33 +++++++++++++++++++
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 7 +++-
> 2 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 3969a7670..c05ceb0be 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -905,6 +905,33 @@ static int
> smu_apply_default_config_table_settings(struct smu_context *smu)
> return smu_set_config_table(smu, &adev->pm.config_table); }
>
> +static int smu_apply_late_quirks(struct smu_context *smu) {
> + struct pci_dev *pdev = smu->adev->pdev;
> + int ret = 0;
> + uint32_t features[2];
> + struct smu_feature_bits feature_mask;
> + uint64_t mask;
> +
> + if (pdev->device == 0x7340 &&
> + pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
> + pdev->subsystem_device == 0x0219) {
> + ret = smu_feature_get_enabled_mask(smu, &feature_mask);
> + if (ret)
> + return ret;
> +
> + smu_feature_bits_to_arr32(&feature_mask, features, 64);
> + features[0] |= BIT(3);
> + mask = ((uint64_t)features[1] << 32) | features[0];
> +
> + ret = smu_set_pp_feature_mask(smu, mask);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static int smu_late_init(struct amdgpu_ip_block *ip_block) {
> struct amdgpu_device *adev = ip_block->adev; @@ -977,6 +1004,12 @@
> static int smu_late_init(struct amdgpu_ip_block *ip_block)
>
> smu_restore_dpm_user_profile(smu);
>
> + ret = smu_apply_late_quirks(smu);
> + if (ret) {
> + dev_err(adev->dev, "Unable to apply late quirks\n");
> + return ret;
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 6dfc3b585..ed67e4bfc 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -349,7 +349,12 @@ navi10_init_allowed_features(struct smu_context *smu)
> (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0,
> 0)) &&
> (adev->rev_id == 0)) &&
> (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
> - smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED,
> FEATURE_DPM_UCLK_BIT);
> + if (!(adev->pdev->device == 0x7340 &&
> + adev->pdev->subsystem_vendor ==
> PCI_VENDOR_ID_APPLE &&
> + adev->pdev->subsystem_device == 0x0219))
> + smu_feature_list_set_bit(smu,
> SMU_FEATURE_LIST_ALLOWED,
> + FEATURE_DPM_UCLK_BIT);
> +
> smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED,
> FEATURE_MEM_VDDCI_SCALING_BIT);
> smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED,
> FEATURE_MEM_MVDD_SCALING_BIT);
> }
> --
> 2.43.0
>
>
