Add a generic MP1 interface to query the status of RAS-related SMU features, including the PMFW EEPROM feature.
Signed-off-by: YiPeng Chai <[email protected]> --- drivers/gpu/drm/amd/ras/core/ras.h | 2 ++ drivers/gpu/drm/amd/ras/core/ras_mp1.c | 13 +++++++++ drivers/gpu/drm/amd/ras/core/ras_mp1.h | 7 +++++ .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c | 28 +++++++++++++++++++ 4 files changed, 50 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/core/ras.h b/drivers/gpu/drm/amd/ras/core/ras.h index fcea457d5cbe..47fa30f94a2a 100644 --- a/drivers/gpu/drm/amd/ras/core/ras.h +++ b/drivers/gpu/drm/amd/ras/core/ras.h @@ -216,6 +216,8 @@ struct ras_mp1_sys_func { int (*mp1_set_debug_mode)(struct ras_core_context *ras_core, bool enable); int (*mp1_send_ras_msg)(struct ras_core_context *ras_core, u32 msg_id, u32 *params, u32 num_params, u32 *read_args, u32 num_read_args); + int (*check_ras_feature_status)(struct ras_core_context *ras_core, + enum ras_mp1_feature_id feature_id, u32 *status); }; struct ras_eeprom_param_config { diff --git a/drivers/gpu/drm/amd/ras/core/ras_mp1.c b/drivers/gpu/drm/amd/ras/core/ras_mp1.c index 0f5140abb6a8..4c180027850f 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_mp1.c +++ b/drivers/gpu/drm/amd/ras/core/ras_mp1.c @@ -183,6 +183,19 @@ int ras_mp1_set_debug_mode(struct ras_core_context *ras_core, bool enable) return mp1->ip_func->set_debug_mode(ras_core, enable); } +int ras_mp1_check_feature_status(struct ras_core_context *ras_core, + enum ras_mp1_feature_id feature_id, u32 *status) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + + if (!mp1->sys_func || + !mp1->sys_func->check_ras_feature_status) + return -EOPNOTSUPP; + + return mp1->sys_func->check_ras_feature_status(ras_core, + feature_id, status); +} + int ras_mp1_sw_init(struct ras_core_context *ras_core) { struct ras_mp1 *mp1 = &ras_core->ras_mp1; diff --git a/drivers/gpu/drm/amd/ras/core/ras_mp1.h b/drivers/gpu/drm/amd/ras/core/ras_mp1.h index 410530fb8ada..b872fc975866 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_mp1.h +++ b/drivers/gpu/drm/amd/ras/core/ras_mp1.h @@ -28,6 +28,11 @@ #define MAX_UE_BANKS_PER_QUERY 12 #define MAX_CE_BANKS_PER_QUERY 12 +enum ras_mp1_feature_id { + RAS_MP1_FEATURE_PMFW_EEPROM, + RAS_MP1_FEATURE_MAX +}; + enum ras_mp1_msg_id { RAS_MP1_MSG_QueryValidMcaCount, RAS_MP1_MSG_McaBankDumpDW, @@ -122,4 +127,6 @@ int ras_mp1_reset_ras_table(struct ras_core_context *ras_core, int ras_mp1_get_record_count(struct ras_core_context *ras_core, u32 *count); int ras_mp1_get_record(struct ras_core_context *ras_core, u32 idx, struct eeprom_err_record *rec); +int ras_mp1_check_feature_status(struct ras_core_context *ras_core, + enum ras_mp1_feature_id feature_id, u32 *status); #endif diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c index eb7ffa354541..d8a446d0179e 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1.c @@ -25,6 +25,10 @@ #include "amdgpu_reset.h" #include "ras.h" +static const enum smu_feature_mask ras_smu_feature_masks[RAS_MP1_FEATURE_MAX] = { + [RAS_MP1_FEATURE_PMFW_EEPROM] = SMU_FEATURE_HROM_EN_BIT, +}; + static const enum smu_message_type ras_smu_msg_maps[RAS_MP1_MSG_MAX] = { [RAS_MP1_MSG_QueryValidMcaCount] = SMU_MSG_QueryValidMcaCount, [RAS_MP1_MSG_McaBankDumpDW] = SMU_MSG_McaBankDumpDW, @@ -49,6 +53,29 @@ static enum smu_message_type return ras_smu_msg_maps[msg_id]; } +static int amdgpu_ras_check_ras_feature_status(struct ras_core_context *ras_core, + enum ras_mp1_feature_id feature_id, u32 *status) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + u32 res = 0; + + if (!status || (feature_id >= RAS_MP1_FEATURE_MAX)) + return -EINVAL; + + if (down_read_trylock(&adev->reset_domain->sem)) { + if (amdgpu_smu_ras_feature_is_enabled(adev, + ras_smu_feature_masks[feature_id])) + res = 1; + up_read(&adev->reset_domain->sem); + } else { + return -RAS_CORE_GPU_IN_MODE1_RESET; + } + + *status = res; + + return 0; +} + static int amdgpu_ras_send_mp1_msg(struct ras_core_context *ras_core, u32 msg_id, u32 *params, u32 num_params, u32 *read_args, u32 num_read_args) { @@ -73,4 +100,5 @@ static int amdgpu_ras_send_mp1_msg(struct ras_core_context *ras_core, u32 msg_id const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func = { .mp1_send_ras_msg = amdgpu_ras_send_mp1_msg, + .check_ras_feature_status = amdgpu_ras_check_ras_feature_status, }; -- 2.43.0
