Check for both the MMIO/KIQ/MES and SDMA pathes.

Signed-off-by: Alex Deucher <[email protected]>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 4acad329aee5a..f1c7bb37cfb8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -724,6 +724,13 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, 
uint32_t vmid,
        struct amdgpu_job *job;
        int r;
 
+       /*
+        * A GPU reset should flush all TLBs anyway, so no need to do
+        * this while one is ongoing.
+        */
+       if (!down_read_trylock(&adev->reset_domain->sem))
+               return;
+
        ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]);
 
        switch (adev->gmc.gart_inv_method) {
@@ -740,13 +747,6 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, 
uint32_t vmid,
 
        if (!adev->mman.buffer_funcs_enabled || vmid ||
            !adev->ib_pool_ready || !ring->sched.ready || use_mmio) {
-               /*
-                * A GPU reset should flush all TLBs anyway, so no need to do
-                * this while one is ongoing.
-                */
-               if (!down_read_trylock(&adev->reset_domain->sem))
-                       return;
-
                if (adev->gmc.flush_tlb_needs_extra_type_2)
                        adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid,
                                                           vmhub, 2);
@@ -784,11 +784,13 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, 
uint32_t vmid,
 
        dma_fence_wait(fence, false);
        dma_fence_put(fence);
+       up_read(&adev->reset_domain->sem);
 
        return;
 
 error_alloc:
        mutex_unlock(&adev->mman.default_entity.lock);
+       up_read(&adev->reset_domain->sem);
        dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r);
 }
 
-- 
2.55.0

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