Hello Aurabindo Pillai,
Commit 7f7d7ea1fa51 ("drm/amd/display: Add new sources for DCN6")
from Jul 22, 2026 (linux-next), leads to the following Smatch static
checker warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn50/dcn50_hwseq.c:641
dcn50_init_hw()
error: we previously assumed 'dc->clk_mgr' could be null (see line 541)
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn50/dcn50_hwseq.c
529 void dcn50_init_hw(struct dc *dc)
530 {
531 struct abm **abms = dc->res_pool->multiple_abms;
532 struct dce_hwseq *hws = dc->hwseq;
533 struct dc_bios *dcb = dc->ctx->dc_bios;
534 struct resource_pool *res_pool = dc->res_pool;
535 unsigned int i;
536 unsigned int edp_num;
537 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
538 uint32_t user_level = MAX_BACKLIGHT_LEVEL;
539 int current_dchub_ref_freq = 0;
540
541 if (dc->clk_mgr && dc->clk_mgr->funcs &&
dc->clk_mgr->funcs->init_clocks) {
^^^^^^^^^^^
Check for NULL
542 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
543
544 // mark dcmode limits present if any clock has distinct
AC and DC values from SMU
545 dc->caps.dcmode_power_limits_present =
dc->clk_mgr->funcs->is_dc_mode_present &&
546
dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr);
547 }
548
549 // Initialize the dccg
550 if (res_pool->dccg->funcs->dccg_init)
551 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
552
553 // Disable DMUB Initialization until IPS state programming is
finalized
554 //if (!dcb->funcs->is_accelerated_mode(dcb)) {
555 // hws->funcs.bios_golden_init(dc);
556 //}
557
558 // Set default OPTC memory power states
559 if (dc->debug.enable_mem_low_power.bits.optc) {
560 // Shutdown when unassigned and light sleep in VBLANK
561 REG_SET_2(ODM_MEM_PWR_CTRL3, 0,
ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
562 }
563
564 if (dc->debug.enable_mem_low_power.bits.vga) {
565 // Power down VGA memory
566 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
567 }
568
569 if (dc->ctx->dc_bios->fw_info_valid) {
570 res_pool->ref_clocks.xtalin_clock_inKhz =
571
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
572
573 if (res_pool->hubbub) {
574
(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
575
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
576
&res_pool->ref_clocks.dccg_ref_clock_inKhz);
577
578 current_dchub_ref_freq =
res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
579
580
(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
581
res_pool->ref_clocks.dccg_ref_clock_inKhz,
582
&res_pool->ref_clocks.dchub_ref_clock_inKhz);
583 } else {
584 // Not all ASICs have DCCG sw component
585 res_pool->ref_clocks.dccg_ref_clock_inKhz =
586
res_pool->ref_clocks.xtalin_clock_inKhz;
587 res_pool->ref_clocks.dchub_ref_clock_inKhz =
588
res_pool->ref_clocks.xtalin_clock_inKhz;
589 }
590 } else
591 ASSERT_CRITICAL(false);
592
593 for (i = 0; i < dc->link_count; i++) {
594 /* Power up AND update implementation according to the
595 * required signal (which may be different from the
596 * default signal on connector).
597 */
598 struct dc_link *link = dc->links[i];
599
600 link->link_enc->funcs->hw_init(link->link_enc);
601
602 /* Check for enabled DIG to identify enabled display */
603 if (link->link_enc->funcs->is_dig_enabled &&
604
link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
605 link->link_status.link_active = true;
606 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
607 if (link->link_enc->funcs->fec_is_active &&
608
link->link_enc->funcs->fec_is_active(link->link_enc))
609 link->fec_state = dc_link_fec_enabled;
610 }
611 }
612
613 /* enable_power_gating_plane before dsc_pg_control because
614 * FORCEON = 1 with hw default value on bootup, resume from s3
615 */
616 if (hws->funcs.enable_power_gating_plane)
617 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
618
619 /* we want to turn off all dp displays before doing detection */
620 dc->link_srv->blank_all_dp_displays(dc);
621
622 /* If taking control over from VBIOS, we may want to optimize
our first
623 * mode set, so we need to skip powering down pipes until we
know which
624 * pipes we want to use.
625 * Otherwise, if taking control is not possible, we need to
power
626 * everything down.
627 */
628 if (dcb->funcs->is_accelerated_mode(dcb) ||
!dc->config.seamless_boot_edp_requested) {
629 /* Disable boot optimizations means power down
everything including PHY, DIG,
630 * and OTG (i.e. the boot is not optimized because we
do a full power down).
631 */
632 if (dc->hwss.enable_accelerated_mode &&
dc->debug.disable_boot_optimizations)
633 dc->hwss.enable_accelerated_mode(dc,
dc->current_state);
634 else
635 hws->funcs.init_pipes(dc, dc->current_state);
636
637 if
(dc->res_pool->hubbub->funcs->allow_self_refresh_control)
638
dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
639
!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
640
--> 641 dcn50_initialize_min_clocks(dc);
^^
Unchecked dereference.
642
643 /* On HW init, allow idle optimizations after pipes
have been turned off.
644 *
645 * In certain D3 cases (i.e. BOCO / BOMACO) it's
possible that hardware state
646 * is reset (i.e. not in idle at the time hw init is
called), but software state
647 * still has idle_optimizations = true, so we must
disable idle optimizations first
648 * (i.e. set false), then re-enable (set true).
649 */
650 dc_allow_idle_optimizations(dc, false);
651 dc_allow_idle_optimizations(dc, true);
652 }
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regards,
dan carpenter
