On GFX 12.1, ring buffers may be mapped with a non-coherently cached memory type. In that case the queue fetch can observe stale packets, since the packet producers (CPU or other GPUs) do not keep the device-side cache coherent.
Set CP_HQD_PQ_CONTROL.SCOPE=3 (SYSTEM) so the queue fetches use system scope and pick up the latest packets. Apply this to compute queue MQDs and to MES-managed queues. Without this, the queue can consume stale packets for long periods, causing severe slowdowns and, in the worst case, application hangs. Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Joseph Greathouse <[email protected]> Signed-off-by: Mukul Joshi <[email protected]> --- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index a69f9b9c5cd6..7459547b7a69 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -1302,6 +1302,7 @@ static int mes_v12_1_mqd_init(struct amdgpu_ring *ring) tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, SCOPE, 3); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c index 60de32cb9ecd..29c20398c60b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c @@ -335,6 +335,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, /* GC 10 removed WPP_CLAMP from PQ Control */ m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | + 3 << CP_HQD_PQ_CONTROL__SCOPE__SHIFT | 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; m->cp_hqd_pq_doorbell_control |= 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; -- 2.55.0
