From: Fangzhi Zuo <[email protected]>
[WHAT]
Folding the MCCS FreeSync checks into the do_mccs block dropped the
other half of the original condition: the check that clears
freesync_capable for HDMI or PCON-in-whitelist sinks that expose no
EDID FreeSync VCP code. That check does not depend on the MCCS caps
and must run regardless of do_mccs.
As a result, when do_mccs is false such a sink without a FreeSync VCP
code is still reported as FreeSync-capable.
[HOW]
Restore the VCP code check outside the do_mccs block so it is
evaluated whether or not MCCS caps were read.
Fixes: ("drm/amd/display: Consult MCCS FreeSync cap only if requested &
supported")
Reviewed-by: Roman Li <[email protected]>
Reviewed-by: Alex Hung <[email protected]>
Signed-off-by: Fangzhi Zuo <[email protected]>
Signed-off-by: George Zhang <[email protected]>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c | 6 ++++++
.../display/amdgpu_dm/tests/amdgpu_dm_connector_test.c | 9 ++++++---
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index bcf0ed4fa589..7ebf7216b499 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@ -3987,6 +3987,12 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector
*connector,
amdgpu_dm_connector->min_vfreq;
}
+ /* HDMI/PCON without an EDID FreeSync VCP code is not FreeSync-capable.
*/
+ if ((sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A ||
+ as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) &&
+ !sink->edid_caps.freesync_vcp_code)
+ freesync_capable = false;
+
/* Handle MCCS */
if (do_mccs) {
dm_helpers_read_mccs_caps(adev->dm.dc->ctx,
amdgpu_dm_connector->dc_link, sink);
diff --git
a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
index ff22e79e7c92..0f7cf32373d3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_connector_test.c
@@ -9783,6 +9783,8 @@ static void dm_test_fs_caps_edp_replay_mode(struct kunit
*test)
*
* On HDMI the CEA extension is handed to the DMCU parser, whose reported
* 24-60Hz range is copied to the connector and published as the monitor range.
+ * The DMCU does not report an EDID FreeSync VCP code, so the connector is not
+ * marked FreeSync-capable.
*/
static void dm_test_fs_caps_hdmi_vsdb(struct kunit *test)
{
@@ -9800,7 +9802,7 @@ static void dm_test_fs_caps_hdmi_vsdb(struct kunit *test)
KUNIT_EXPECT_EQ(test, ctx->aconnector->max_vfreq, 60);
KUNIT_EXPECT_EQ(test, connector->display_info.monitor_range.min_vfreq,
24);
KUNIT_EXPECT_EQ(test, connector->display_info.monitor_range.max_vfreq,
60);
- KUNIT_EXPECT_TRUE(test, dm_test_fs_caps_capable(ctx));
+ KUNIT_EXPECT_FALSE(test, dm_test_fs_caps_capable(ctx));
}
/**
@@ -9827,7 +9829,8 @@ static void dm_test_fs_caps_hdmi_no_vsdb(struct kunit
*test)
* @test: The KUnit test context
*
* A whitelisted protocol converter re-parses the AMD VSDB, enables SDP v1.3
- * packing and adopts the converter adaptive sync type.
+ * packing and adopts the converter adaptive sync type. Without an EDID
+ * FreeSync VCP code, the connector is not marked FreeSync-capable.
*/
static void dm_test_fs_caps_pcon_whitelist(struct kunit *test)
{
@@ -9850,7 +9853,7 @@ static void dm_test_fs_caps_pcon_whitelist(struct kunit
*test)
(int)FREESYNC_TYPE_PCON_IN_WHITELIST);
KUNIT_EXPECT_EQ(test, ctx->aconnector->min_vfreq, 24);
KUNIT_EXPECT_EQ(test, ctx->aconnector->max_vfreq, 60);
- KUNIT_EXPECT_TRUE(test, dm_test_fs_caps_capable(ctx));
+ KUNIT_EXPECT_FALSE(test, dm_test_fs_caps_capable(ctx));
}
/**
--
2.55.0
