Re: [PATCH] drm/amdkfd: Preserve v1 in gfx12.1 trap workaround

[Lancelot SIX]

On 18/09/2026 03:13, Jay Cornwall wrote:

If MODE.DST_VGPR_MSB != MODE.SRC0_VGPR_MSB upon trap entry then
v1 would be trashed.

Adjust workaround to prefetch random address 0xFFFFFFFFxxxxxxxx.
This is unused address space on gfx12.1 besides the TBA and TMA
which are harmless to prefetch.

Also remove unused WAVE_START exception handler.

Hi,

This looks reasonable to me.

Reviewed-by: Lancelot Six <lancelot....@amd.com>

Best,
Lancelot.

Signed-off-by: Jay Cornwall <jay.cornw...@amd.com>
Cc: Joseph Greathouse <joseph.greatho...@amd.com>
Cc: Lancelot Six <lancelot....@amd.com>
Cc: Vladimir Indic <vladimir.in...@amd.com>
---
  .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h    | 16 ++++----------
  .../amd/amdkfd/cwsr_trap_handler_gfx12.asm    | 21 +++----------------
  2 files changed, 7 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h 
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index 8cf3527dc156..73889430d2e4 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -4601,19 +4601,11 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = {
  };

static const uint32_t cwsr_trap_gfx12_1_0_hex[] = {

-       0xbfa00001, 0xbfa003f1,
+       0xbfa00001, 0xbfa003e1,
        0xb0804009, 0xb8f8f804,
-       0xb8faf811, 0xbf0d887a,
-       0xbfa10008, 0xb9800211,
-       0x00000000, 0xbeee0180,
-       0x7e020280, 0xee17406e,
-       0x00040000, 0x00000001,
-       0xbe804a6c, 0xbefa007e,
-       0xbefe0081, 0xd760007b,
-       0x00010101, 0xbeee0180,
-       0x7e020280, 0xee17406e,
-       0x00040000, 0x00000001,
-       0xd7610001, 0x0001007b,
+       0xbefa007e, 0xbefe0081,
+       0xbeee0180, 0xee17406e,
+       0x00040000, 0x00000000,
        0xbefe007a, 0x9178ff78,
        0x00008c00, 0xb8fbf811,
        0xbf0c877b, 0xbfa20002,
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm 
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm
index 233ed8b6d122..9d54a77da6cd 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm
@@ -246,28 +246,13 @@ L_SKIP_RESTORE:
        s_getreg_b32    s_save_state_priv, hwreg(HW_REG_WAVE_STATE_PRIV)        
//save STATUS since we will change SCC

#if VMEM_ON_TRAP_ENTRY_WA

-       s_getreg_b32    ttmp14, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV)
-       s_bitcmp1_b32   ttmp14, SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT
-       s_cbranch_scc0  L_NOT_WAVE_START
-
-       s_setreg_imm32_b32      hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, 
SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT, 1), 0
-
-       s_mov_b64       [ttmp2, ttmp3], 0
-       v_mov_b32       v1, 0
-       global_prefetch_b8      v1, [ttmp2, ttmp3] scope:SCOPE_SE th:TH_LOAD_RT
-
-       s_rfe_b64       [ttmp0, ttmp1]
-
-L_NOT_WAVE_START:
        s_mov_b32       ttmp14, exec_lo
        s_mov_b32       exec_lo, 1
-       v_readlane_b32  ttmp15, v1, 0

- s_mov_b64 [ttmp2, ttmp3], 0

-       v_mov_b32       v1, 0
-       global_prefetch_b8      v1, [ttmp2, ttmp3] scope:SCOPE_SE th:TH_LOAD_RT
+       // No-op prefetch to random address 0xFFFFFFFFxxxxxxxx, faults or hits 
TBA/TMA.
+       s_mov_b64       [ttmp2, ttmp3], 0xFFFFFFFF00000000
+       global_prefetch_b8      v0, [ttmp2, ttmp3] scope:SCOPE_SE th:TH_LOAD_RT

- v_writelane_b32 v1, ttmp15, 0

        s_mov_b32       exec_lo, ttmp14
  #endif