From: ZhenGuo Yin <[email protected]> On some SR-IOV VFs RCC_CONFIG_MEMSIZE reads back 0. Fall back to RCC_HW_DEBUG for the frame buffer size in the nbif get_memsize() callback and in the early-init paths that read the register directly. Only VFs that read back 0 are affected.
Signed-off-by: ZhenGuo Yin <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 16 ++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/nbif_v7_10.c | 8 +++++++- 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 2034754d6af74..59294028f0690 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -144,6 +144,7 @@ MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); /* Note: These registers are consistent across all the SOCs */ #define mmIP_DISCOVERY_VERSION 0x16A00 #define mmRCC_CONFIG_MEMSIZE 0xde3 +#define mmRCC_HW_DEBUG 0x10c01 #define mmMP0_SMN_C2PMSG_33 0x16061 #define mmMM_INDEX 0x0 #define mmMM_INDEX_HI 0x6 @@ -289,6 +290,17 @@ static int hw_id_map[MAX_HWIP] = { [ATU_HWIP] = ATU_HWID, }; +static u32 amdgpu_discovery_get_config_memsize(struct amdgpu_device *adev) +{ + u32 memsize = RREG32(mmRCC_CONFIG_MEMSIZE); + + /* Fall back to RCC_HW_DEBUG when RCC_CONFIG_MEMSIZE reads 0 on a VF. */ + if (!memsize && amdgpu_sriov_vf(adev)) + memsize = RREG32(mmRCC_HW_DEBUG); + + return memsize; +} + static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, bool *is_tmr_in_sysmem) { @@ -313,7 +325,7 @@ static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, } } - vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); + vram_size = amdgpu_discovery_get_config_memsize(adev); if (vram_size == U32_MAX) return -ENXIO; else if (!vram_size) @@ -2323,7 +2335,7 @@ static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, struct binary_header_v2 bhdrv2; uint16_t checksum; - vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; + vram_size = (uint64_t)amdgpu_discovery_get_config_memsize(adev) << 20; pos = vram_size - DISCOVERY_TMR_OFFSET; amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index a454c6f12d38d..681a9904a79e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -47,6 +47,7 @@ } while (0) #define mmRCC_CONFIG_MEMSIZE 0xde3 +#define mmRCC_HW_DEBUG 0x10c01 const char *amdgpu_virt_dynamic_crit_table_name[] = { "IP DISCOVERY", @@ -1068,6 +1069,9 @@ int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) return 0; vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); + /* Fall back to RCC_HW_DEBUG when RCC_CONFIG_MEMSIZE reads 0 on a VF. */ + if (!vram_size) + vram_size = RREG32(mmRCC_HW_DEBUG); if (!vram_size || vram_size == U32_MAX) return -EINVAL; vram_size <<= 20; diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v7_10.c b/drivers/gpu/drm/amd/amdgpu/nbif_v7_10.c index 9022454aa74ec..3cdbb79906470 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbif_v7_10.c +++ b/drivers/gpu/drm/amd/amdgpu/nbif_v7_10.c @@ -60,7 +60,13 @@ static void nbif_v7_10_mc_access_enable(struct amdgpu_device *adev, bool enable) static u32 nbif_v7_10_get_memsize(struct amdgpu_device *adev) { - return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); + u32 vram_size = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); + + /* Fall back to RCC_HW_DEBUG when RCC_CONFIG_MEMSIZE reads 0 on a VF. */ + if (!vram_size && amdgpu_sriov_vf(adev)) + vram_size = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_HW_DEBUG); + + return vram_size; } static void nbif_v7_10_sdma_doorbell_range(struct amdgpu_device *adev, -- 2.55.0
