AMD General The compute vm and npa vm are all built on top of the base amdgpu vm initialized by amdgpu_vm_init(). need_tlb_fence should be initialized correctly from the beginning. However, because of an incorrect setting in sdma_v7_1_sw_init(), causing need_tlb_fence to be initialized incorrectly:
vm->need_tlb_fence = amdgpu_userq_enabled(&adev->ddev); Therefore, I do not believe this issue is a regression introduced by commit aac13f6eded6 (“drm/amdgpu: Pin page tables in NPA VMs”). I recommend correcting the SDMA v7.1 user-queue configuration to ensure that need_tlb_fence is initialized correctly and to prevent similar issues in the future. Regards, Hawking From: Kuehling, Felix <[email protected]> Sent: Sunday, September 20, 2026 3:26 PM To: Zhang, Hawking <[email protected]>; Zhang, Horatio <[email protected]>; [email protected] Cc: Ma, Le <[email protected]>; Joshi, Mukul <[email protected]>; Deucher, Alexander <[email protected]> Subject: Re: [PATCH] drm/amdgpu: skip the PASID TLB fence for the UALink NPA VM Regardless of SDMA userq support, this patch still looks reasonable to me. The TLB fence doesn't make sense for NPA VMs. We handle TLB flushes for NPA page table updates explicitly in the amdgpu_ualink code. Feel free to submit this patch with Reviewed-by: Felix Kuehling <[email protected]><mailto:[email protected]> On 2026-09-20 10:41, Zhang, Hawking wrote: AMD General Hi @Zhang, Horatio<mailto:[email protected]>, I think the issue is caused by the following code in sdma_v7_1_sw_init, which incorrectly marks amdgpu user queues as enabled for SDMA 7.1 as long as the CONFIG_DRM_AMDGPU_NAVI3X_USERQ is enabled. Since SDMA 7.1 does not amdgpu user queues (it only supports rocm user queues), could you please remove this code and check whether the issue still occurs? #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; #endif Regards, Hawking -----Original Message----- From: Zhang, Horatio <[email protected]><mailto:[email protected]> Sent: Sunday, September 20, 2026 5:47 AM To: [email protected]<mailto:[email protected]> Cc: Zhang, Hawking <[email protected]><mailto:[email protected]>; Ma, Le <[email protected]><mailto:[email protected]>; Kuehling, Felix <[email protected]><mailto:[email protected]>; Joshi, Mukul <[email protected]><mailto:[email protected]>; Deucher, Alexander <[email protected]><mailto:[email protected]> Subject: RE: [PATCH] drm/amdgpu: skip the PASID TLB fence for the UALink NPA VM AMD General Gentle Ping ... Best regards, Horatio -----Original Message----- From: Horatio Zhang <[email protected]<mailto:[email protected]>> Sent: Thursday, September 17, 2026 6:05 PM To: [email protected]<mailto:[email protected]> Cc: Zhang, Hawking <[email protected]<mailto:[email protected]>>; Ma, Le <[email protected]<mailto:[email protected]>>; Zhang, Horatio <[email protected]<mailto:[email protected]>> Subject: [PATCH] drm/amdgpu: skip the PASID TLB fence for the UALink NPA VM amdgpu_vm_make_npa() builds the UALink NPA VM on top of amdgpu_vm_make_compute(), which unconditionally sets need_tlb_fence. That flag makes amdgpu_vm_tlb_flush() queue an asynchronous PASID based TLB invalidation after every page table update. The NPA VM is created by the driver itself in amdgpu_ualink_manager_start() and never gets a PASID assigned, so vm->pasid stays 0, which MES cannot resolve on the MMHUB. The vm->invalidation never completes and MES stays unresponsive for the rest of the probe: amdgpu: MES(0, 0) failed to respond to msg=INVALIDATE_TLBS The invalidation is not needed in the first place. An NPA VM is bound to the reserved NPA VMID and amdgpu_ualink_flush_tlb() already invalidates that VMID on the MMHUB after every mapping change. Clear need_tlb_fence for NPA VMs. Fixes: aac13f6eded6 ("drm/amdgpu: Pin page tables in NPA VMs") Signed-off-by: Horatio Zhang <[email protected]<mailto:[email protected]>> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 68d668dfe4f8..e255b5100362 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2793,6 +2793,7 @@ int amdgpu_vm_make_npa(struct amdgpu_device *adev, struct amdgpu_vm *vm) return r; vm->is_npa = true; + vm->need_tlb_fence = false; return 0; } -- 2.43.0
