Ignore this patch. I sent the wrong patch out.
On Wed, Sep 23, 2026 at 3:26 PM Alex Deucher <[email protected]> wrote: > > Use the new reset critical section accessors for debugfs, sysfs, > and the INFO IOCTL to provide proper mutual exclusivity > to hardware with respect the GPU resets. > > Signed-off-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 8 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 + > drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 212 ++++++++++++++++++++ > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 +- > 4 files changed, 221 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > index 1b7673d239dbb..ba1f224fb99aa 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > @@ -1780,7 +1780,7 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file > *m, void *unused) > } > > /* Avoid accidently unparking the sched thread during GPU reset */ > - r = down_write_killable(&adev->reset_domain->sem); > + r = amdgpu_reset_domain_access_write_start(adev); > if (r) { > pm_runtime_put_autosuspend(dev->dev); > return r; > @@ -1811,7 +1811,7 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file > *m, void *unused) > drm_sched_wqueue_start(&ring->sched); > } > > - up_write(&adev->reset_domain->sem); > + amdgpu_reset_domain_access_write_end(adev); > > pm_runtime_put_autosuspend(dev->dev); > > @@ -2043,7 +2043,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 > val) > return -ENOMEM; > > /* Avoid accidently unparking the sched thread during GPU reset */ > - r = down_read_killable(&adev->reset_domain->sem); > + r = amdgpu_reset_domain_access_read_start(adev); > if (r) > goto pro_end; > > @@ -2084,7 +2084,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 > val) > /* restart the scheduler */ > drm_sched_wqueue_start(&ring->sched); > > - up_read(&adev->reset_domain->sem); > + amdgpu_reset_domain_access_read_end(adev); > > pro_end: > kfree(fences); > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > index f2f179421c4da..a4ed540409ba7 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > @@ -776,7 +776,11 @@ int amdgpu_info_ioctl(struct drm_device *dev, void > *data, struct drm_file *filp) > return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; > } > case AMDGPU_INFO_TIMESTAMP: > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return -EFAULT; > ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); > + amdgpu_reset_domain_access_read_end(adev); > return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; > case AMDGPU_INFO_FW_VERSION: { > struct drm_amdgpu_info_firmware fw_info; > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > index df5bbdab1ea39..88f6afc9c72fa 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > @@ -31,6 +31,7 @@ > #include "amdgpu_display.h" > #include "hwmgr.h" > #include <linux/power_supply.h> > +#include "amdgpu_reset.h" > #include "amdgpu_smu.h" > > #define amdgpu_dpm_notify_ac_dc(adev) \ > @@ -46,10 +47,14 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool > low) > if (!pp_funcs->get_sclk) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return 0; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, > low); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -62,10 +67,14 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool > low) > if (!pp_funcs->get_mclk) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return 0; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, > low); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -523,12 +532,16 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, > enum amd_pp_sensors senso > return -EINVAL; > > if (pp_funcs && pp_funcs->read_sensor) { > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, > sensor, > data, > size); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > } > > return ret; > @@ -1021,7 +1034,10 @@ void amdgpu_dpm_get_current_power_state(struct > amdgpu_device *adev, > goto out; > } > > + if (amdgpu_reset_domain_access_read_start(adev)) > + goto out; > *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); > + amdgpu_reset_domain_access_read_end(adev); > if (*state < POWER_STATE_TYPE_DEFAULT || > *state > POWER_STATE_TYPE_INTERNAL_3DPERF) > *state = adev->pm.dpm.user_state; > @@ -1054,12 +1070,15 @@ enum amd_dpm_forced_level > amdgpu_dpm_get_performance_level(struct amdgpu_device > if (!pp_funcs) > return AMD_DPM_FORCED_LEVEL_AUTO; > > + if (amdgpu_reset_domain_access_read_start(adev)) > + return AMD_DPM_FORCED_LEVEL_AUTO; > mutex_lock(&adev->pm.mutex); > if (pp_funcs->get_performance_level) > level = > pp_funcs->get_performance_level(adev->powerplay.pp_handle); > else > level = adev->pm.dpm.forced_level; > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return level; > } > @@ -1091,6 +1110,7 @@ int amdgpu_dpm_force_performance_level(struct > amdgpu_device *adev, > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK > | > AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK > | > AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; > + int ret; > > if (!pp_funcs || !pp_funcs->force_performance_level) > return 0; > @@ -1108,15 +1128,23 @@ int amdgpu_dpm_force_performance_level(struct > amdgpu_device *adev, > > if (adev->asic_type == CHIP_RAVEN) { > if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && > level == AMD_DPM_FORCED_LEVEL_MANUAL) > amdgpu_gfx_off_ctrl(adev, false); > else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL > && > level != AMD_DPM_FORCED_LEVEL_MANUAL) > amdgpu_gfx_off_ctrl(adev, true); > + amdgpu_reset_domain_access_read_end(adev); > } > } > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > + > if (!(current_level & profile_mode_mask) && (level & > profile_mode_mask)) > amdgpu_dpm_enter_umd_state(adev); > else if ((current_level & profile_mode_mask) && > @@ -1142,6 +1170,7 @@ int amdgpu_dpm_force_performance_level(struct > amdgpu_device *adev, > adev->pm.dpm.forced_level = level; > > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return 0; > } > @@ -1155,10 +1184,14 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device > *adev, > if (!pp_funcs->get_pp_num_states) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, > states); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1173,11 +1206,15 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device > *adev, > if (!pp_funcs->dispatch_tasks) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, > task_id, > user_state); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1203,6 +1240,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, > char *table, > !pp_funcs->get_pp_table) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, > &pptable); > @@ -1213,6 +1253,7 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, > char *table, > memcpy(table, pptable, ret); > } > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1228,12 +1269,16 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct > amdgpu_device *adev, > if (!pp_funcs->set_fine_grain_clk_vol) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, > type, > input, > size); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1249,12 +1294,16 @@ int amdgpu_dpm_odn_edit_dpm_table(struct > amdgpu_device *adev, > if (!pp_funcs->odn_edit_dpm_table) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, > type, > input, > size); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1270,12 +1319,16 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device > *adev, > if (!pp_funcs->emit_clock_levels) > return -ENOENT; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, > type, > buf, > offset); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1289,10 +1342,14 @@ int amdgpu_dpm_set_ppfeature_status(struct > amdgpu_device *adev, > if (!pp_funcs->set_ppfeature_status) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, > ppfeature_masks); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1305,10 +1362,14 @@ int amdgpu_dpm_get_ppfeature_status(struct > amdgpu_device *adev, char *buf) > if (!pp_funcs->get_ppfeature_status) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, > buf); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1323,11 +1384,15 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device > *adev, > if (!pp_funcs->force_clock_level) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, > type, > mask); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1340,9 +1405,13 @@ int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) > if (!pp_funcs->get_sclk_od) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1350,14 +1419,19 @@ int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) > int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > + int ret; > > if (is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > if (pp_funcs->set_sclk_od) > pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > if (amdgpu_dpm_dispatch_task(adev, > AMD_PP_TASK_READJUST_POWER_STATE, > @@ -1377,9 +1451,13 @@ int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) > if (!pp_funcs->get_mclk_od) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1387,14 +1465,19 @@ int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) > int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > + int ret; > > if (is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > if (pp_funcs->set_mclk_od) > pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > if (amdgpu_dpm_dispatch_task(adev, > AMD_PP_TASK_READJUST_POWER_STATE, > @@ -1415,10 +1498,14 @@ int amdgpu_dpm_get_power_profile_mode(struct > amdgpu_device *adev, > if (!pp_funcs->get_power_profile_mode) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, > buf); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1432,11 +1519,15 @@ int amdgpu_dpm_set_power_profile_mode(struct > amdgpu_device *adev, > if (!pp_funcs->set_power_profile_mode) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, > input, > size); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1451,6 +1542,9 @@ ssize_t amdgpu_dpm_get_gpu_metrics(struct amdgpu_device > *adev, void *buf, > if (!pp_funcs->get_gpu_metrics) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, > &table); > @@ -1459,6 +1553,7 @@ ssize_t amdgpu_dpm_get_gpu_metrics(struct amdgpu_device > *adev, void *buf, > memcpy(buf, table, ret); > } > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1472,10 +1567,14 @@ ssize_t amdgpu_dpm_get_pm_metrics(struct > amdgpu_device *adev, void *pm_metrics, > if (!pp_funcs->get_pm_metrics) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, > size); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1489,10 +1588,14 @@ int amdgpu_dpm_get_fan_control_mode(struct > amdgpu_device *adev, > if (!pp_funcs->get_fan_control_mode) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, > fan_mode); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1506,10 +1609,14 @@ int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device > *adev, > if (!pp_funcs->set_fan_speed_pwm) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, > speed); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1523,10 +1630,14 @@ int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device > *adev, > if (!pp_funcs->get_fan_speed_pwm) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, > speed); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1540,10 +1651,14 @@ int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device > *adev, > if (!pp_funcs->get_fan_speed_rpm) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, > speed); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1557,10 +1672,14 @@ int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device > *adev, > if (!pp_funcs->set_fan_speed_rpm) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, > speed); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1574,10 +1693,14 @@ int amdgpu_dpm_set_fan_control_mode(struct > amdgpu_device *adev, > if (!pp_funcs->set_fan_control_mode) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, > mode); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1593,12 +1716,16 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device > *adev, > if (!pp_funcs->get_power_limit) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, > limit, > pp_limit_level, > power_type); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1613,10 +1740,14 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device > *adev, > if (!pp_funcs->set_power_limit) > return -EINVAL; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, > limit_type, limit); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1628,9 +1759,12 @@ int amdgpu_dpm_is_cclk_dpm_supported(struct > amdgpu_device *adev) > if (!is_support_sw_smu(adev)) > return false; > > + if (amdgpu_reset_domain_access_read_start(adev)) > + return false; > mutex_lock(&adev->pm.mutex); > cclk_dpm_supported = is_support_cclk_dpm(adev); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return (int)cclk_dpm_supported; > } > @@ -1639,14 +1773,19 @@ int > amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade > struct seq_file *m) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > + int ret; > > if (!pp_funcs->debugfs_print_current_performance_level) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > > pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, > m); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return 0; > } > @@ -1661,11 +1800,15 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct > amdgpu_device *adev, > if (!pp_funcs->get_smu_prv_buf_details) > return -ENOSYS; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, > addr, > size); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1728,11 +1871,15 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device > *adev, > !pp_funcs->set_pp_table) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, > buf, > size); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1764,10 +1911,14 @@ int amdgpu_dpm_display_configuration_change(struct > amdgpu_device *adev, > if (!pp_funcs->display_configuration_change) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = > pp_funcs->display_configuration_change(adev->powerplay.pp_handle, > input); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1782,11 +1933,15 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device > *adev, > if (!pp_funcs->get_clock_by_type) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, > type, > clocks); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1800,10 +1955,14 @@ int > amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, > if (!pp_funcs->get_display_mode_validation_clocks) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = > pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, > clocks); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1818,11 +1977,15 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct > amdgpu_device *adev, > if (!pp_funcs->get_clock_by_type_with_latency) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = > pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, > type, > clocks); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1837,11 +2000,15 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct > amdgpu_device *adev, > if (!pp_funcs->get_clock_by_type_with_voltage) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = > pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, > type, > clocks); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1855,10 +2022,14 @@ int > amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, > if (!pp_funcs->set_watermarks_for_clocks_ranges) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = > pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, > clock_ranges); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1872,10 +2043,14 @@ int amdgpu_dpm_display_clock_voltage_request(struct > amdgpu_device *adev, > if (!pp_funcs->display_clock_voltage_request) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = > pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, > clock); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1889,10 +2064,14 @@ int amdgpu_dpm_get_current_clocks(struct > amdgpu_device *adev, > if (!pp_funcs->get_current_clocks) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, > clocks); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1904,9 +2083,12 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct > amdgpu_device *adev) > if (!pp_funcs->notify_smu_enable_pwe) > return; > > + if (amdgpu_reset_domain_access_read_start(adev)) > + return; > mutex_lock(&adev->pm.mutex); > pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > } > > int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, > @@ -1918,10 +2100,14 @@ int amdgpu_dpm_set_active_display_count(struct > amdgpu_device *adev, > if (!pp_funcs->set_active_display_count) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, > count); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1935,10 +2121,14 @@ int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct > amdgpu_device *adev, > if (!pp_funcs->set_min_deep_sleep_dcefclk) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return ret; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, > clock); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1951,10 +2141,13 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct > amdgpu_device *adev, > if (!pp_funcs->set_hard_min_dcefclk_by_freq) > return; > > + if (amdgpu_reset_domain_access_read_start(adev)) > + return; > mutex_lock(&adev->pm.mutex); > pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, > clock); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > } > > void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, > @@ -1965,10 +2158,13 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct > amdgpu_device *adev, > if (!pp_funcs->set_hard_min_fclk_by_freq) > return; > > + if (amdgpu_reset_domain_access_read_start(adev)) > + return; > mutex_lock(&adev->pm.mutex); > pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, > clock); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > } > > int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device > *adev, > @@ -1980,10 +2176,14 @@ int > amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, > if (!pp_funcs->display_disable_memory_clock_switch) > return 0; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return 0; > mutex_lock(&adev->pm.mutex); > ret = > pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, > > disable_memory_clock_switch); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -1997,10 +2197,14 @@ int > amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, > if (!pp_funcs->get_max_sustainable_clocks_by_dc) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return 0; > mutex_lock(&adev->pm.mutex); > ret = > pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, > max_clocks); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -2015,11 +2219,15 @@ enum pp_smu_status > amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, > if (!pp_funcs->get_uclk_dpm_states) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return 0; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, > clock_values_in_khz, > num_states); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > @@ -2033,10 +2241,14 @@ int amdgpu_dpm_get_dpm_clock_table(struct > amdgpu_device *adev, > if (!pp_funcs->get_dpm_clock_table) > return -EOPNOTSUPP; > > + ret = amdgpu_reset_domain_access_read_start(adev); > + if (ret) > + return 0; > mutex_lock(&adev->pm.mutex); > ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, > clock_table); > mutex_unlock(&adev->pm.mutex); > + amdgpu_reset_domain_access_read_end(adev); > > return ret; > } > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > index 7fee5c88b6736..f16e512e23de3 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c > @@ -27,7 +27,6 @@ > #include "amdgpu_drv.h" > #include "amdgpu_pm.h" > #include "amdgpu_dpm.h" > -#include "amdgpu_reset.h" > #include "atom.h" > #include <linux/pci.h> > #include <linux/hwmon.h> > @@ -144,7 +143,7 @@ static int amdgpu_pm_dev_state_check(struct amdgpu_device > *adev, bool runpm) > bool runpm_check = runpm ? adev->in_runpm : false; > bool full_init = (adev->init_lvl->level == AMDGPU_INIT_LEVEL_DEFAULT); > > - if (amdgpu_in_reset(adev) || !full_init) > + if (!full_init) > return -EBUSY; > > if (adev->in_suspend && !runpm_check) > -- > 2.55.0 >
