MGCG registers are PF-only. Skip programming them under SR-IOV.
Signed-off-by: Jane Jian <[email protected]>
Signed-off-by: YuBiao Wang <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 4f6eac30b235..c9de9216bd65 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -2417,8 +2417,10 @@ static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device
*adev, uint16_t xcc_mask
return r;
}
- gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, false,
- xcc_id, true);
+ /* MGCG is device wide and owned by the PF */
+ if (!amdgpu_sriov_vf(adev))
+ gfx_v12_1_xcc_update_medium_grain_clock_gating(adev,
false,
+ xcc_id,
true);
/* GFX CGCG and LS is disabled by rlc fw */
gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
@@ -2440,8 +2442,9 @@ static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device
*adev, uint16_t xcc_mask
if (r)
return r;
}
- gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, true,
- xcc_id, true);
+ if (!amdgpu_sriov_vf(adev))
+ gfx_v12_1_xcc_update_medium_grain_clock_gating(adev,
true,
+ xcc_id,
true);
}
return 0;
--
2.34.1
