[why] VF timestamp queries need a TSC sample independent of CP/MES. The SMUIO path is not safe on VF.
[how] Capture via RLC_CAPTURE_GPU_CLOCK_COUNT and read the consecutive count registers with amdgpu_mes_rreg64(). v3: check errors returned by amdgpu_mes_rreg64() Signed-off-by: Victor Zhao <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index d6f70d33201a0..83be620d7204b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -3168,10 +3168,37 @@ static int gfx_v12_1_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } +static uint64_t gfx_v12_1_get_rlc_gpu_clock_counter(struct amdgpu_device *adev) +{ + uint64_t clock = 0; + uint32_t reg; + + if (!down_read_trylock(&adev->reset_domain->sem)) + return 0; + if (amdgpu_device_skip_hw_access(adev) || + !adev->mes.ring[0].sched.ready) + goto unlock_reset; + + mutex_lock(&adev->gfx.gpu_clock_mutex); + WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); + reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), + regRLC_GPU_CLOCK_COUNT_LSB); + if (amdgpu_mes_rreg64(adev, reg, 0, &clock)) + clock = 0; + mutex_unlock(&adev->gfx.gpu_clock_mutex); + +unlock_reset: + up_read(&adev->reset_domain->sem); + return clock; +} + static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev) { uint64_t clock = 0; + if (amdgpu_sriov_vf(adev)) + return gfx_v12_1_get_rlc_gpu_clock_counter(adev); + if (adev->smuio.funcs && adev->smuio.funcs->get_gpu_clock_counter) clock = adev->smuio.funcs->get_gpu_clock_counter(adev); -- 2.50.1
