On A+A, HBM is reached at a host physical address, so VRAM mappings need the system-memory path. That is true for both an SR-IOV VF and a passthrough VM; native PF A+A keeps the mmhub/sysvm path.
Add AMDGPU_VIRT_VRAM_IS_SPM and amdgpu_virt_vram_is_spm() so later patches can identify SPM-backed VRAM without repeating the cap test. v2: - Rename the helper to amdgpu_virt_vram_is_spm(); it only tests AMDGPU_VIRT_VRAM_IS_SPM. - Set the cap in ip_early_init when an SR-IOV VF or passthrough dGPU has no FB BAR0, after AMD_IS_APU is known. Signed-off-by: Zhigang Luo <[email protected]> Signed-off-by: Fangsheng Huang <[email protected]> Signed-off-by: YuBiao Wang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 44091ac12fa9..96165b1b3e6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2085,6 +2085,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) if (!(adev->flags & AMD_IS_APU)) { parent = amdgpu_device_find_parent(adev); adev->has_pr3 = parent ? pci_pr3_present(parent) : false; + + if ((amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) && + !pci_resource_len(adev->pdev, 0)) + adev->virt.caps |= AMDGPU_VIRT_VRAM_IS_SPM; } adev->pm.pp_feature = amdgpu_pp_feature_mask; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 9957241bdf59..a2c1aa838737 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -32,6 +32,7 @@ #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ +#define AMDGPU_VIRT_VRAM_IS_SPM (1 << 6) /* FB BAR0 is absent; VRAM is SPM */ /* flags for indirect register access path supported by rlcg for sriov */ #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) @@ -406,6 +407,9 @@ struct amdgpu_video_codec_info; #define amdgpu_passthrough(adev) \ ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) +#define amdgpu_virt_vram_is_spm(adev) \ +((adev)->virt.caps & AMDGPU_VIRT_VRAM_IS_SPM) + #define amdgpu_sriov_vf_mmio_access_protection(adev) \ ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) -- 2.43.0
