Ping.
On Thu, Sep 24, 2026 at 07:01:28 UTC, YuBiao Wang wrote: > Golden register init, the SDMA RB command switch setup, the GFXHUB > L2 protection fault controls and the guest-side FB_LOCATION programming > all touch registers a VF does not own, so leave them to the PF. > > Signed-off-by: YuBiao Wang <[email protected]> > Acked-by: Lijo Lazar <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c | 24 +++-------------------- > drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 3 ++- > 3 files changed, 7 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > index db541939555b..4f6eac30b235 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c > @@ -2665,7 +2665,8 @@ static int gfx_v12_1_hw_init(struct amdgpu_ip_block > *ip_block) > if (r) > return r; > > - gfx_v12_1_init_golden_registers(adev); > + if (!amdgpu_sriov_vf(adev)) > + gfx_v12_1_init_golden_registers(adev); > > gfx_v12_1_constants_init(adev); > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c > index 7fa451b373fc..b13967a1c8fb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c > @@ -482,27 +482,6 @@ static void gfxhub_v12_1_xcc_program_invalidation(struct > amdgpu_device *adev, > static int gfxhub_v12_1_xcc_gart_enable(struct amdgpu_device *adev, > uint32_t xcc_mask) > { > - uint32_t i; > - > - if (amdgpu_sriov_vf(adev)) { > - /* GCMC_VM_FB_LOCATION_BASE/TOP are VF copy registers > - * VBIO post does not program them at boot up phase > - * Need driver to program them from guest side */ > - for_each_inst(i, xcc_mask) { > - WREG32_SOC15(GC, GET_INST(GC, i), > - regGCMC_VM_FB_LOCATION_BASE_LO32, > - lower_32_bits(adev->gmc.vram_start >> 24)); > - WREG32_SOC15(GC, GET_INST(GC, i), > - regGCMC_VM_FB_LOCATION_BASE_HI32, > - upper_32_bits(adev->gmc.vram_start >> 24)); > - WREG32_SOC15(GC, GET_INST(GC, i), > - regGCMC_VM_FB_LOCATION_TOP_LO32, > - lower_32_bits(adev->gmc.vram_end >> 24)); > - WREG32_SOC15(GC, GET_INST(GC, i), > - regGCMC_VM_FB_LOCATION_TOP_HI32, > - upper_32_bits(adev->gmc.vram_end >> 24)); > - } > - } > /* GART Enable. */ > gfxhub_v12_1_xcc_init_gart_aperture_regs(adev, xcc_mask); > gfxhub_v12_1_xcc_init_system_aperture_regs(adev, xcc_mask); > @@ -576,6 +555,9 @@ static void > gfxhub_v12_1_xcc_set_fault_enable_default(struct amdgpu_device *adev > u32 tmp; > int i; > > + if (amdgpu_sriov_vf(adev)) > + return; > + > for_each_inst(i, xcc_mask) { > tmp = RREG32_SOC15(GC, GET_INST(GC, i), > regGCVM_L2_PROTECTION_FAULT_CNTL_LO32); > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c > index 321c67e01443..d1e09acc684a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c > @@ -1397,7 +1397,8 @@ static int sdma_v7_1_hw_init(struct amdgpu_ip_block > *ip_block) > > inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); > > - sdma_v7_1_rb_cmd_switch(adev, inst_mask); > + if (!amdgpu_sriov_vf(adev)) > + sdma_v7_1_rb_cmd_switch(adev, inst_mask); > > r = sdma_v7_1_inst_start(adev, inst_mask); > if (r)
