block GPU PCI bar access during mode1 reset on gfx12, to resolve the random mode1 reset hang issue.
Signed-off-by: Yifan Zhang <[email protected]> --- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 29 ++++++++++++------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 072d9c4e202d..25b9085ead71 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -2078,21 +2078,30 @@ static int smu_v14_0_2_set_df_cstate(struct smu_context *smu, static int smu_v14_0_2_mode1_reset(struct smu_context *smu) { + struct amdgpu_device *adev = smu->adev; + u16 saved_cmd, cmd; int ret = 0; ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset); - if (!ret) { - if (amdgpu_emu_mode == 1) { - msleep(50000); - } else { - /* disable mmio access while doing mode 1 reset*/ - smu->adev->no_hw_access = true; - /* ensure no_hw_access is globally visible before any MMIO */ - smp_mb(); - msleep(1000); - } + if (ret) + return ret; + + pci_read_config_word(adev->pdev, PCI_COMMAND, &saved_cmd); + cmd = saved_cmd & ~PCI_COMMAND_MEMORY; + pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); + + if (amdgpu_emu_mode == 1) { + msleep(50000); + } else { + /* disable mmio access while doing mode 1 reset*/ + smu->adev->no_hw_access = true; + /* ensure no_hw_access is globally visible before any MMIO */ + smp_mb(); + msleep(1000); } + pci_write_config_word(adev->pdev, PCI_COMMAND, saved_cmd); + return ret; } -- 2.43.0
