gfx_v12_1_get_xccs_per_xcp() supplies the compute partition layout that gfx_v12_1_cp_resume() needs on a VF. Once VFI is enabled the VF reaches registers through RLCG, which cannot access the GFX_IMU registers, so the GFX_IMU_PARTITION_SWITCH read stops working. Take the same field from RLC_IMU_AID_CONFIG instead, and read it with a direct MMIO access rather than RREG32_SOC15, which would route back into the RLCG path.
Signed-off-by: YuBiao Wang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 13 +++++++++++++ .../drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h | 2 ++ .../drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h | 4 ++++ 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 1cf175aac4de..4498e253846f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -703,6 +703,19 @@ static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev) u32 reg_data; /* the register data is expected to be the same on all instances */ + if (amdgpu_sriov_vf(adev)) { + /* + * RLCG cannot access the GFX_IMU registers, so take the field + * from RLC_IMU_AID_CONFIG and read it without going through + * the RLCG path. + */ + reg_data = RREG32_NO_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), + regRLC_IMU_AID_CONFIG)); + + return REG_GET_FIELD(reg_data, RLC_IMU_AID_CONFIG, + TOTAL_XCCS_IN_XCP); + } + reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), regGFX_IMU_PARTITION_SWITCH_SHADOW); diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h index dbd497d9fac1..249ffb38c05a 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h @@ -6649,6 +6649,8 @@ #define regRLC_IMU_MISC_BASE_IDX 1 #define regRLC_IMU_RESET_VECTOR 0x4e17 #define regRLC_IMU_RESET_VECTOR_BASE_IDX 1 +#define regRLC_IMU_AID_CONFIG 0x4e18 +#define regRLC_IMU_AID_CONFIG_BASE_IDX 1 // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcsdec diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h index 68dfafd8d027..f4a21a8c4e1b 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h @@ -20866,6 +20866,10 @@ #define RLC_IMU_RESET_VECTOR__VECTOR_MASK 0x000000FCL #define RLC_IMU_RESET_VECTOR__RESERVED_MASK 0xFFFFFF00L +//RLC_IMU_AID_CONFIG +#define RLC_IMU_AID_CONFIG__TOTAL_XCCS_IN_XCP__SHIFT 0x2 +#define RLC_IMU_AID_CONFIG__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL + // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcsdec //RLC_RLCS_DEC_START -- 2.34.1
